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R5F52108ADFK Datasheet(PDF) 9 Page - Renesas Technology Corp |
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R5F52108ADFK Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 146 page  R01DS0041EJ0090 Rev.0.90 Page 9 of 144 Aug 10, 2011 RX210 Group 1. Overview Under development Preliminary document Specifications in this document are tentative and subject to change. 1.4 Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1 / 4) Classifications Pin Name I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. VCL Input Connect this pin to VSS via a 0.1 F capacitor. The capacitor should be placed close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V). Clock XTAL Output Pins for connecting a crystal resonator. An external clock signal can be input through the EXTAL pin. EXTAL Input BCLK Output Outputs the external bus clock for external devices. XCIN Input Input/output pins for the subclock generation circuit. Connect a crystal resonator between XCIN and XCOUT. XCOUT Output Operating mode control MD Input Pins for setting the operating mode. The signal levels on this pin must not be changed during operation. System control RES# Input Reset signal input pin. This LSI enters the reset state when this signal goes low. CAC CACREF Input Input pin for the measuring circuit for clock frequency precision. On-chip emulator FINED I/O FINE interface pin. FINEC Input Clock pin for FINE interface. Address bus A0 to A23 Output Output pins for the address. Data bus D0 to D15 I/O Input and output pins for the bidirectional data bus. Bus control RD# Output Strobe signal which indicates that reading from the external bus interface space is in progress. WR# Output Strobe signal which indicates that writing to the external bus interface space is in progress, in single-write strobe mode. WR0#, WR1# Output Strobe signals which indicate that either group of data bus pins (D7 to D0, and D15 to D8) is valid in writing to the external bus interface space, in byte strobe mode. BC0#, BC1# Output Strobe signals which indicate that either group of data bus pins (D7 to D0 and D15 to D8) is valid in access to the external bus interface space, in single-write strobe mode. CS0# to CS3# Output Select signals for areas 0 to 3. WAIT# Input Input pins for wait request signals in access to the external space. ALE Output Address latch signal when address/data multiplexed bus is selected. Interrupt (ICU) NMI Input Non-maskable interrupt request signal. IRQ0 to IRQ7 Input Interrupt request signals. |
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