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R5F5631DCDLC Datasheet(PDF) 2 Page - Renesas Technology Corp

Part # R5F5631DCDLC
Description  Renesas MCUs
Download  108 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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R01DS0098EJ0090 Rev.0.90
Page 2 of 106
Dec 27, 2011
RX63N Group, RX631 Group
1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications in outline, and table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages in the
RX63N/RX631 Group.
Table 1.1
Outline of Specifications (1/5)
Classification
Module/Function
Description
CPU
CPU
 Maximum operating frequency: 100 MHz
 32-bit RX CPU
 Minimum instruction execution time: One instruction per state (cycle of the system
clock)
 Address space: 4-Gbyte linear
 Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
 Basic instructions: 73
 Floating-point instructions: 8
 DSP instructions: 9
 Addressing modes: 10
 Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
 On-chip 32-bit multiplier: 32 x 32  64 bits
 On-chip divider: 32 / 32  32 bits
 Barrel shifter: 32 bits
FPU
 Single precision (32-bit) floating point
 Data types and floating-point exceptions in conformance with the IEEE754 standard
Memory
ROM
 ROM capacity: 2 Mbytes (max.)
 Two on-board programming modes
Boot mode (The user area is programmable via the SCI and USB.)
User program mode
 Parallel programmer mode (for off-board programming)
RAM
RAM capacity: 128 Kbytes (max.)
E2 data flash
Data ROM capacity: 32 Kbytes
MCU operating modes
Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled
expansion mode (software switching)
Clock
Clock generation circuit
 Main clock oscillator, subclock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and IWDT-dedicated on-chip oscillator
 Main-clock oscillation stoppage detection
 Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLK):
Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): Up to 50 MHz
Reset
Pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer reset,
watchdog timer reset, deep software standby reset, and software reset
Voltage detection circuit
When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.


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