Micrel, Inc.

SY89540U

December 2007

M9999-120607-C

4

Pin Description

Pin Number

Pin Name

Pin Function

17, 15,

10, 8

4, 2

41, 39

IN0, /IN0,

IN1, /IN1,

IN2, /IN2,

IN3, /IN3

Differential Inputs: These input pairs are the differential signal inputs to the

device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin

of a pair internally terminates to a VT pin through 50Ω. Note that these inputs

will default to an indeterminate state if left open. Please refer to the "Input

Interface Applications" section for more details.

16, 9,

3, 40

VT0, VT1,

VT2, VT3

Input Termination Center-Tap: Each side of the differential input pair terminates

to a VT pin. The VT pins provide a center-tap to a termination network for

maximum interface flexibility. See "Input Interface Applications" section for more

details.

14,

11,

1,

42

VREF_AC0,

VREF_AC1,

VREF_AC2,

VREF_AC3

coupling the inputs (IN, /IN). Connect VREF_AC to the VT pin. Bypass each

VREF-AC pin with a 0.01

μF low ESR capacitor. See "Input Interface

Applications" section for more details.

18, 19

SIN0,

SIN1

These single-ended TTL/CMOS-compatible inputs address the data inputs.

Note that these inputs are internally connected to a 25kΩ pull-up resistor and

will default to a logic HIGH state if left open.

38, 37

SOUT0,

SOUT1

These single-ended TTL/CMOS-compatible inputs address the data outputs.

Note that these inputs are internally connected to a 25kΩ pull-up resistor and

will default to logic HIGH state if left open.

5, 7

CONF,

LOAD

These single-ended TTL/CMOS-compatible inputs control the transfer of the

addresses to the internal multiplexers. See "Address Tables" and "Timing

Diagram" sections for more details. Note that these inputs are internally

connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left

open.

Configuration Sequence

1. Load: Loads configuration into buffer, while Configuration Buffer holds

existing switch configuration.

2. Configuration: Loads new configuration into the Configuration Buffer and

updates switch configuration.

Buffer Mode

The SY89540U defaults to buffer mode (IN to Q) if the load and configuration

control signals are not exercised.

23, 24,

26, 27,

29, 30,

32, 33

Q0, /Q0,

Q1, /Q1,

Q2, /Q2,

Q3, /Q3,

Differential Outputs: These LVDS output pairs are the outputs of the device.

Please refer to the truth table below for details. Unused output pairs may be left

open. Each output is designed to drive 350mV into 100Ω across the pair.

6, 22, 25,

28, 31, 34

VCC

Positive power supply. Bypass with 0.1

μF//0.01μF low ESR capacitors and

12, 13, 20,

21,35, 36,

43, 44

GND,

Exposed pad

Ground. GND and EPad must both be connected to the same ground.