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SY58608UMG Datasheet(PDF) 1 Page - Micrel Semiconductor

Part # SY58608UMG
Description  3.2Gbps Precision, 1:2 LVDS Fanout Buffer
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY58608UMG Datasheet(HTML) 1 Page - Micrel Semiconductor

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SY58608U
3.2Gbps Precision, 1:2 LVDS Fanout Buffer
with Internal Termination and Fail Safe Input
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2006
M9999-102706-A
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY58608U is a 2.5V, high-speed, fully differential
1:2 LVDS fanout buffer optimized to provide two
identical output copies with less than 20ps of skew and
less than 10psPP total jitter. The SY58608U can process
clock signals as fast as 2GHz or data patterns up to
3.2Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mVPP) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
voltage reference (VREF-AC) is provided to bias the VT pin.
The outputs are 325mV LVDS, with rise/fall times
guaranteed to be less than 100ps.
The SY58608U operates from a 2.5V ±5% supply and is
guaranteed over the full industrial temperature range (–
40°C to +85°C). For applications that require CML or
LVPECL outputs, consider Micrel’s SY58606U and
SY58607U, 1:2 fanout buffers with 400mV and 800mV
output swings respectively. The SY58608U is part of
Micrel’s high-speed, Precision Edge
® product line.
Data sheets and support documentation can be found
on Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge
®
Features
• Precision 1:2, 325mV LVDS fanout buffer
• Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps throughput
– <300ps propagation delay (IN-to-Q)
– <20ps within-device skew
– <100ps rise/fall times
• Fail Safe Input
Prevents outputs from oscillating when input is
invalid
• Ultra-low jitter design
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter
– <1psRMS random jitter
– <10psPP deterministic jitter
• High-speed LVDS outputs
• 2.5V ±5% power supply operation
• Industrial temperature range: –40°C to +85°C
• Available in 16-pin (3mm x 3mm) QFN package
Applications
• All SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution
• Backplane distribution
Markets
• DataCom
• Telecom
• Storage
• ATE
• Test and Measurement


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