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SY58040U Datasheet(PDF) 3 Page - Micrel Semiconductor |
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SY58040U Datasheet(HTML) 3 Page - Micrel Semiconductor |
3 / 12 page 3 SY58040U Micrel, Inc. M9999-103009 hbwhelp@micrel.com or (408) 955-1690 PACkAGE/ORDERINGINFORMATION OrderingInformation(1) Package Operating Package PartNumber Type Range Marking SY58040UMY(3) QFN-44 Industrial SY58040U Pb-Free Pb-Free bar-line indicator SY58040UMYTR(2, 3) QFN-44 Industrial SY58040U Pb-Free Pb-Free bar-line indicator Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs. PinNumber PinName PinFunction 17, 15, IN0, /IN0 Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept 10, 8, IN1, /IN1 AC or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin 4, 2, IN2, /IN2 through 50Ω. Note that these inputs will default to an indeterminate state if left open. Please refer to 41, 39 IN3, /IN3 the “Input Interface Applications” section for more details. 16, 9, VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT 3, 40 VT2, VT3 pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. 14, VRef_AC0 Reference Voltage: This output biases to VCC–1.2V. It is used when AC coupling the inputs. 11, VRef_AC1 Connect VRef-AC output pin to the VT input pin. Bypass each VRef-AC pin with a 0.01µF low ESR 1, VRef_AC2 capacitor to VCC. See “Input Interface Applications” section for more details. 42 VRef_AC3 18 SIN0 These single-ended TTL/CMOS-compatible inputs address the data inputs. Note that these inputs 19 SIN1 are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. 38 SOUT0 These single-ended TTL/CMOS-compatible inputs address the data outputs. Note that these inputs 37 SOUT1 are internally connected to a 25kΩ pullup resistor and will default to a logic HIGH state if left open. 5 CONF, These single-ended TTL/CMOS compatible inputs control the transfer of the addresses to the 7 LOAD internal multiplexers. See “Address Tables” and “Timing Diagram” sections for more details. Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. Configuration Sequence 1. Load: Loads configuration into buffer, while Configuration Buffer holds existing switch configuration. 2. Configuration: Loads new configuration into the Configuration Buffer and updates switch configuration. Buffer Mode The SY58040U defaults to buffer mode (IN-to-Q) if the load and configuration control signals are floating. 23, 24, Q0, /Q0, Differential Outputs: These CML output pairs are the outputs of the device. Please refer to the truth 26, 27, Q1, /Q1, table below for details. Unused output pairs may be left open. Each output is designed to drive 29, 30 Q2, /Q2, 400mV into 100Ω across the pair, or 50Ω to VCC. 32, 33 Q3, /Q3, 6, 22, 25, VCC Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to each 28, 31, 34 VCC pin. 12, 13, 20, 21, GND, Ground. GND and EPad must both be connected to most negative potential of chip ground. 35, 36, 43, 44 Exposed pad PIN DESCRIPTION 44-PinQFN(QFN-44) |
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