CCD area image sensors

S7030/S7031 series

10

Speci cations of built-in TE-cooler (Typ. vacuum condition)

Pin connections

Parameter

Symbol

Condition

S7031-0906S/-0907S

S7031-1006S/-1007S

Unit

Internal resistance

Rint

Ta=25 °C

2.5

1.2

1.5

3.0

A

Maximum voltage

3.8

3.6

V

Qmax

3.4

5.1

W

Maximum temperature

of heat radiating side

-70

70

°C

*

20: If the current greater than this value ows into the thermoelectric cooler, the heat absorption begins to decrease due to the Joule

heat. It should be noted that this value is not the damage threshold value. To protect the thermoelectric cooler and maintain stable

operation, the supply current should be less than 60% of this maximum current.

*

21: Temperature of the cooling side of thermoelectric cooler

*

22: Temperature of the heat radiating side of thermoelectric cooler

*

23: This is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler when the maximum

current is supplied to the unit.

Pin

No.

S7030 series

S7031 series

Remark

(standard operation)

Symbol

Function

Symbol

Function

1

RD

Reset drain

RD

Reset drain

+12 V

2

OS

Output transistor source

OS

Output transistor source

3

OD

Output transistor drain

OD

Output transistor drain

+20 V

4

OG

Output gate

OG

Output gate

+3 V

5

SG

Summing gate

SG

Summing gate

Same pulse as P2H

6-

-

7-

-

8

P2H

CCD horizontal register clock-2

P2H

CCD horizontal register clock-2

9

P1H

CCD horizontal register clock-1

P1H

CCD horizontal register clock-1

10

IG2H

Test point (horizontal input gate-2)

IG2H

Test point (horizontal input gate-2)

-8 V

11

IG1H

Test point (horizontal input gate-1)

IG1H

Test point (horizontal input gate-1)

-8 V

12

ISH

Test point (horizontal input source)

ISH

Test point (horizontal input source)

Connect to RD

13

Transfer gate

Transfer gate

Same pulse as P2V

14

P2V

CCD vertical register clock-2

P2V

CCD vertical register clock-2

15

P1V

CCD vertical register clock-1

P1V

CCD vertical register clock-1

16

-

Th1

Thermistor

17

-

Th2

Thermistor

18

-

P-

TE-cooler-

19

-

P+

TE-cooler+

20

SS

Substrate (GND)

SS

Substrate (GND)

GND

21

ISV

Test point (vertical input source)

ISV

Test point (vertical input source)

Connect to RD

22

IG2V

Test point (vertical input gate-2)

IG2V

Test point (vertical input gate-2)

-8 V

23

IG1V

Test point (vertical input gate-1)

IG1V

Test point (vertical input gate-1)

-8 V

24

RG

Reset gate

RG

Reset gate

*

19: Isolation gate between vertical register and horizontal register. In standard operation, TG should be applied the same pulse as P2V.