MCM6226BB

5

MOTOROLA FAST SRAM

6226BB–15

6226BB–17

6226BB–20

6226BB–25

6226BB–35

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

15

—

17

—

20

—

25

—

35

—

ns

5

Address Setup Time

tAVWL

0

—

0

—

0

—

0

—

0

—

ns

Address Valid to End of Write

tAVWH

12

—

14

—

15

—

17

—

20

—

ns

Write Pulse Width

tWLWH,

tWLEH

12

—

14

—

15

—

17

—

20

—

ns

Data Valid to End of Write

tDVWH

7

—

8

—

9

—

10

—

11

—

ns

Data Hold TIme

tWHDX

0

—

0

—

0

—

0

—

0

—

ns

Write Low to Data High–Z

tWLQZ

—

6

—

7

—

7

—

8

—

8

ns

6, 7, 8

Write High to Output Active

tWHQX

5

—

5

—

5

—

5

—

5

—

ns

6, 7, 8

Write Recovery Time

tWHAX

0

—

0

—

0

—

0

—

0

—

ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-

tention conditions during read and write cycles.

3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.

4. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.

5. All timings are referenced from the last valid address to the first transitioning address.

6. Transition is measured

± 500 mV from steady–state voltage with load of Figure 1b.

7. This parameter is sampled and not 100% tested.

8. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.

tAVWH

tWLQZ

tWHAX

tDVWH

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

DATA VALID

HIGH–Z

HIGH–Z

tAVAV

tAVWL

tWLEH

tWHDX

tWLWH

tWHQX