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HYB39S256400T-8B Datasheet(PDF) 9 Page - Siemens Semiconductor Group |
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HYB39S256400T-8B Datasheet(HTML) 9 Page - Siemens Semiconductor Group |
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9 / 56 page  HYB 39S256400/800/160T 256 MBit Synchronous DRAM Semiconductor Group 9 1998-10-01 Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Notes 1. V = Valid, X = Don’t Care, L = Low Level, H = High Level. 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BS0, BS1 signals. 4. Device state is Full Page Burst operation. 5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock suspend mode. Operation Device State CKE n-1 CKE n DQM BS0 BS1 AP = A10 Addr CS RAS CAS WE Bank Active Idle 3 H XXVVV L L H H Bank Precharge Any H X X VLXL L H L Precharge All Any H X X X H X L L H L Write Active 3 H X X VLVL H L L Write with Auto Precharge Active 3 HX X VHV L H L L Read Active 3 H X X V L V LHLH Read with Auto Precharge Active 3 H X X V H V LHLH Mode Register Set Idle H XXVVV LLLL No Operation Any H XXXXX L H H H Burst Stop Active 4 H XXXXX L H H L Device Deselect Any H XXXXX H XXX Auto Refresh Idle H H XXXX L L L H Self Refresh Entry Idle H L XXXX L L L H Self Refresh Exit Idle (Self Refr.) L H XXXX H XXX LH H X Clock Suspend Entry Active H L XXXXXXXX Power Down Entry (Precharge or active standby) Idle Active 5 H L XXXX H XXX LH H X Clock Suspend Exit Active L H XXXXXXXX Power Down Exit Any (Power Down) L H XXXX H XXX LH HL Data Write/Output Enable Active H X L XXXXXXX Data Write/Output Disable Active H X H XXXXXXX |
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