HYB3117400BJ-50 datasheet(7/26 Pages) SIEMENS

Part #	HYB3117400BJ-50

Description	4M x 4-Bit Dynamic RAM 2k & 4k Refresh

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Manufacturer	SIEMENS [Siemens Semiconductor Group]

Direct Link	http://www.siemens.com/

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7 / 26 page

HYB 5116(7)400BJ-50/-60

HYB 3116(7)400BJ/BT-50/-60

4M

× 4 DRAM

Semiconductor Group

7

1998-10-01

DC Characteristics (cont’d)

T

A = 0 to 70 °C, VSS = 0 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

2k

4k

Common Parameters

Input leakage current

(0 V

≤ V

IH ≤ VCC + 0.3 V, all other pins = 0 V)

I

I(L)

–10

10

µA

1

Output leakage current

(DO is disabled, 0 V

≤ V

OUT ≤ VCC + 0.3 V)

I

O(L)

–10

10

µA

1

Average

V

CC supply current

-50 ns version

-60 ns version

(RAS, CAS, address cycling:

t

RC = tRC MIN.)

I

CC1

–

80

70

50

40

mA

2, 3, 4

Standby

V

CC supply current (RAS = CAS = VIH)

I

CC2

–

2

mA

–

Average

V

CC supply current, during RAS-only refresh

cycles

-50 ns version

-60 ns version

(RAS cycling, CAS =

V

IH, tRC = tRC MIN.)

I

CC3

–

80

70

50

40

mA

2, 4

Average

V

CC supply current,during fast page mode

-50 ns version

-60 ns version

(RAS =

V

IL, CAS, address cycling: tPC = tPC MIN.)

I

CC4

–

25

20

mA

2, 3, 4

Standby

V

CC supply current

(RAS = CAS =

V

CC – 0.2 V)

I

CC5

–1

mA

1

Average

V

CC supply current, during CAS-before-RAS

refresh mode

-50 ns version

-60 ns version

(RAS, CAS cycling:

t

RC = tRC MIN.)

I

CC6

–

80

70

50

40

mA

2, 4

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