Semiconductor Group

10

HYB5117805BSJ-50/-60/-70

2M x 8-EDO DRAM

Notes:

1) All voltages are referenced to

2)

3)

4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during

a hyper page mode (EDO) cycle

5) An initial pause of 200

µs is required after power-up followed by 8 RAS cycles of which at least one cycle has

to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,

a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume

t

7)

V

IH

measured between

V

8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined

by the latter of tRAC, tCAC, tAA,tCPA, tOEA. tCAC is measured from tristate.

last.

13) Either

t

14) Either

t

the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above

sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.

16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge

in read-write cycles.

17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM

operation:

If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR

refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.

If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the

refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately

after exit from Self Refresh