HYB 514175BJ-50/-55/-60

256k

× 16 EDO-DRAM

Semiconductor Group

9

1998-10-01

Notes

1. All voltages are referenced to

V

2.

I

3.

I

4. Address can be changed once or less while RAS =

V

or less during a hyper page mode (EDO) cycle

5. An initial pause of 200

µs is required after power-up followed by 8 RAS cycles of which at least

one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using

the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of

8 RAS cycles are required.

6. AC measurements assume

t

7.

V

are also measured between

V

8. Measured with the specified current load and 100 pF at

V

time is determined by the latter of

t

9. Operation within the

t

a reference point only. If

t

controlled by

t

10.Operation within the

t

a reference point only. If

t

controlled by

t

11.Either

t

12.

t

are not referenced to output voltage levels.

t

CAS, whichever occurs last.

13.Either

t

14.Either

t

15.

t

sheet as electrical characteristics only. If

t

data out pin will remain open-circuit (high impedance) through the entire cycle; if

t

contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the

condition of I/O (at access time) is indeterminated.

16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE

leading edge in read-write cycles.