MAX5816 datasheet(6/32 Pages) MAXIM | Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC with Internal Reference and I2C Interface

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MAX5816 Datasheet(PDF) 6 Page - Maxim Integrated Products

Part #	MAX5816

Description	Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC with Internal Reference and I2C Interface

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Manufacturer	MAXIM [Maxim Integrated Products]

Direct Link	https://www.maximintegrated.com/en.html

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Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC

with Internal Reference and I2C Interface

MAX5816

Maxim Integrated Products 6

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 2.7V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical values are at

TA = +25NC.) (Note 2)

Note 2: Limits are 100% production tested at TA = +25°C and/or TA = +125°C. Limits over the operating temperature range and

relevant supply voltage range are guaranteed by design and characterization. Typical values are at TA = +25°C and are

not guaranteed.

Note 3: DC Performance is tested without load.

Note 4: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.

Note 5: Gain and offset tested at code 4065 and 30, respectively with VREF = VDD.

Note 6: Subject to zero and full-scale error limits and VREF settings.

Note 7: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.

Note 8: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will

be ignored.

Note 9: All channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDD.

Note 10:Guaranteed by design.

Note 11:An unconnected condition on the ADDR pin is sensed via a resistive pullup and pulldown operation; for proper operation,

the ADDR pin should be tied to VDD, GND, or left unconnected with minimal capacitance.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

I2C TIMING CHARACTERISTICS (SCL, SDA)

SCL Clock Frequency

fSCL

400

kHz

Bus Free Time Between a STOP

and a START Condition

tBUF

1.3

F

s

Hold Time Repeated for a

START Condition

tHD;STA

0.6

F

s

SCL Pulse Width Low

tLOW

1.3

F

s

SCL Pulse Width High

tHIGH

0.6

F

s

Setup Time for Repeated START

Condition

tSU;STA

0.6

F

s

Data Hold Time

tHD;DAT

0

900

ns

Data Setup Time

tSU;DAT

100

ns

SDA and SCL Receiving

Rise Time

tr

20 +

CB/10

300

ns

SDA and SCL Receiving

Fall Time

tf

20 +

CB/10

300

ns

SDA Transmitting Fall Time

tf

20 +

CB/10

250

ns

Setup Time for STOP Condition

tSU;STO

0.6

F

s

Bus Capacitance Allowed

CB

10

400

pF

Pulse Width of Suppressed Spike

tsp

50

ns

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