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MAX5813AUD+T Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX5813AUD+T Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 30 page Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface MAX5813/MAX5814/MAX5815 Maxim Integrated Products 6 ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Low Voltage (Note 11) VIL 2.2V < VDDIO < 5.5V 0.3 x VDDIO V 1.8V < VDDIO < 2.2V 0.2 x VDDIO Hysteresis Voltage VH 0.15 V Input Leakage Current IIN VIN = 0V or VDDIO (Note 11) Q 0.1 Q 1 F A Input Capacitance (Note 10) CIN 10 pF ADDR_ Pullup/Pulldown Strength RPU, RPD (Note 12) 30 50 90 kI DIGITAL OUTPUT (SDA) Output Low Voltage VOL ISINK = 3mA 0.2 V I2C TIMING CHARACTERISTICS (SCL, SDA, LDAC, CLR) SCL Clock Frequency fSCL 400 kHz Bus Free Time Between a STOP and a START Condition tBUF 1.3 F s Hold Time Repeated for a START Condition tHD;STA 0.6 F s SCL Pulse Width Low tLOW 1.3 F s SCL Pulse Width High tHIGH 0.6 F s Setup Time for Repeated START Condition tSU;STA 0.6 F s Data Hold Time tHD;DAT 0 900 ns Data Setup Time tSU;DAT 100 ns SDA and SCL Receiving Rise Time tr 20 + CB/10 300 ns SDA and SCL Receiving Fall Time tf 20 + CB/10 300 ns SDA Transmitting Fall Time tf 20 + CB/10 250 ns Setup Time for STOP Condition tSU;STO 0.6 F s Bus Capacitance Allowed CB VDD = 2.7V to 5.5V 10 400 pF Pulse Width of Suppressed Spike tsp 50 ns CLR Removal Time Prior to a Recognized START tCLRSTA 100 ns CLR Pulse Width Low tCLPW 20 ns LDAC Pulse Width Low tLDPW 20 ns SCLK Rise to LDAC Fall to Hold tLDH Applies to execution edge 400 ns |
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