MAX5825 datasheet(6/35 Pages) MAXIM | Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface

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MAX5825 Datasheet(PDF) 6 Page - Maxim Integrated Products

Part #	MAX5825

Description	Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface

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Manufacturer	MAXIM [Maxim Integrated Products]

Direct Link	https://www.maximintegrated.com/en.html

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6 / 35 page

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Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered

Output DACs with Internal Reference and I2C Interface

MAX5823/MAX5824/MAX5825

Maxim Integrated Products 6

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical

values are at TA = +25NC.) (Note 3)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Low Voltage (Note 11)

VIL

(All inputs except

M/Z)

2.2V < VDDIO < 5.5V

0.3 x

VDDIO

V

1.8V < VDDIO < 2.2V

0.2 x

VDDIO

V

2.7V < VDD < 5.5V (for M/Z)

0.3 x

VDD

Input Leakage Current

IIN

VIN = 0V or VDDIO, all inputs except M/Z

(Note 11)

Q

0.1

Q

1

F

A

VIN = 0V or VDD, for M/Z (Note 11)

Input Capacitance (Note 10)

CIN

10

pF

Hysteresis Voltage

VH

0.15

V

ADDR_ Pullup/Pulldown Strength

RPU, RPD

(Note 12)

30

50

90

kI

DIGITAL OUTPUT (SDA, IRQ)

Output Low Voltage

VOL

ISINK = 3mA

0.2

V

Output Inactive Leakage

IOFF

IRQ only, see IIN for SDA

Q

0.1

Q

1

F

A

Output Inactive Capacitance

COFF

IRQ only, see CIN for SDA

10

pF

WATCHDOG TIMER CHARACTERISTICS

Watchdog Timer Period

tWDOSC

VDD = 3V, TA = +25°C

0.95

1

1.05

ms

Watchdog Timer Period Supply

Drift

VDD = 2.7V to 5.5V, TA = +25°C

0.6

%/V

Watchdog Timer Period

Temperature Drift

VDD = 3V

0.0375

%/°C

I2C TIMING CHARACTERISTICS (SCL, SDA, LDAC, CLR)

SCL Clock Frequency

fSCL

400

kHz

Bus Free Time Between a STOP

and a START Condition

tBUF

1.3

F

s

Hold Time Repeated for a START

Condition

tHD;STA

0.6

F

s

SCL Pulse Width Low

tLOW

1.3

F

s

SCL Pulse Width High

tHIGH

0.6

F

s

Setup Time for Repeated START

Condition

tSU;STA

0.6

F

s

Data Hold Time

tHD;DAT

0

900

ns

Data Setup Time

tSU;DAT

100

ns

SDA and SCL Receiving

Rise Time

tR

20 +

CB/10

300

ns

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