Semiconductor Group

10

HYB 514405BJ/BLJ-50/-60/-70

1M x 4 EDO - DRAM

Notes:

2)

3)

a hyper page mode (EDO) cycle

5) An initial pause of 200

µs is required after power-up followed by 8 RAS cycles of which at least one cycle has

to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,

a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume

t

7)

measured between

last.

13) Either

t

14) Either

t

the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above

sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.

16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge

in read-write cycles.