MCM62Y308

6

MOTOROLA FAST SRAM

READ/WRITE CYCLE TIMING DIAGRAM

tGHQZ

(NOTE 3)

tKHQV

tGVKH (NOTE 4)

NOTE: THIS TIMING DIAGRAM ALSO SHOWS THE FUNCTIONALITY OF THE PART

tKHQV

tKHWEX

tWEVKH

Din4

Din3

tDVKH

tKHDX

Din2

Din1

Din0

tWEVKH

tKHWEX

tWRVKH

tKHWRX

tKHREX

tRRVKH

tKHRRX

tREVKH

tKHQZ (NOTE 2)

HIGH–Z

tKLKH

tKHKL

tKHKH

tGLQV (NOTE 3)

D0 – D7

WR

WE

RR

RE

G

K

tKHGX (NOTE 4)

HIGH–Z

RRR,

WRR

RRF,

WRF

tKHRFV (NOTE 1)

tKHRFV

tKHRRRX, tKHWRRX

tWRRVKH, tRRRVKH

Qout4

Qout2

Qout1

Qout0

Q0 – Q7

tKHREX

tREVKH

1. Roll–Over Outputs assert high when counters reach their initial value. This timing diagram shows the relationship between the roll–over

output and reset pin only.

2. The outputs High–Z from a clock high edge when the upper three bits of the Read Address Counter do not match the 3 ID Expansion bits.

3. tGLQV and tGHQZ only apply when G is programmed as Asynchronous. (See TAP LDCONT instruction.)

4. tGVKH and tKHGX only apply when G is programmed as synchronous.