Programmable DC-Balanced

21-Bit Serializers

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11

To obtain DC balance on the data channels, the paral-

lel input data is inverted or not inverted, depending on

the sign of the digital sum at the word boundary. Two

complementary bits are appended to each group of 7

parallel input data bits to indicate to the MAX9210/

MAX9214 deserializers whether the data bits are invert-

ed (Figure 11). The deserializer restores the original

state of the parallel data. The LVDS clock signal alter-

nates duty cycles of 4/9 and 5/9, which maintains DC

balance. Figure 12 shows the non-DC-balanced mode

inputs mapped to LVDS outputs.

DCA0

DCB1

DCA1

DCB2

DCA2

CYCLE N + 1

CYCLE N

CYCLE N - 1

TxIN2

TxIN6

TxIN3

TxIN4

TxIN5

TxIN9

TxIN13

TxIN10

TxIN11

TxIN12

TxIN2

TxIN3

TxIN4

DCA0

TxIN5

TxIN6

DCB0

TxIN9

TxIN10

TxIN11

DCA1

TxIN12

TxIN13

DCB1

TxIN16

TxIN17

TxIN18

DCA2

TxIN19

TxIN20

DCB2

TxIN0

TxIN1

TxIN7

TxIN8

TxIN14

TxIN15

TxIN16

TxIN20

TxIN17

TxIN18

TxIN19

DCB0

TxCLK OUT-

TxOUT1

TxOUT0

TxOUT2

TxIN1

TxIN8

TxIN15

TxIN0

TxIN7

TxIN14

TxCLK OUT+

Figure 11. DC-Balanced Mode Inputs Mapped to LVDS Outputs

2.0V

3.0V

HIGH-Z

DIFFERENTIAL 0

3.6V

TxOUT_, TxCLK OUT

TxCLK IN

PWRDWN

TPPLS

Figure 9. PLL Set Time

TxOUT_, TxCLK OUT

TxCLK IN

PWRDWN

HIGH-Z

0.8V

TPDD

Figure 10. Power-Down Delay