AZ100LVEL32

ECL/PECL

 2 Divider

1630 S. STAPLEY DR., SUITE 127

 MESA, ARIZONA 85204  USA  (480) 962-5881  FAX (623) 505-2414

www.azmicrotek.com

ARIZONA MICROTEK, INC.

FEATURES



Operating Range of 3.0V to 5.5V



470ps Propagation Delay



3.0+ GHz Toggle Frequency



High Bandwidth Output Transitions



Direct Replacement for ON

Semiconductor MC100EL/LVEL32



>2 kV HBM ESD Protection



Additional ESD Data Available on

Arizona Microtek Website

DESCRIPTION

The AZ100LVEL32 is an integrated

÷2 divider. The reset pin is asynchronous and is asserted on the rising edge.

Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of

multiple LVEL32’s in a system.

¯¯¯¯ differential

input pair. The input signal is then fed to the other CLK/CLK

0.01

F capacitor.

NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

1

4

3

2

6

5

7

8

R

÷2

RESET

CLK

CLK

Q

Q

PIN DESCRIPTION

PIN

FUNCTION

CLK, CLK

¯¯¯

Clock Inputs

RESET

Asynchronous Reset

Reference Voltage Output

Q, Q

¯

Data Outputs

Positive Supply

Negative Supply

PACKAGE AVAILABILITY

PACKAGE

PART NUMBER

MARKING

NOTES

SOIC 8 Green /

RoHS Compliant /

Lead (Pb) Free

AZ100LVEL32DG

AZM100G

LVEL32

1,2

MSOP 8 Green /

RoHS Compliant /

Lead (Pb) Free

AZ100LVEL32TG

AZHG

LV32

1,2

MLP 8 (2x2) Green

/ RoHS Compliant /

Lead (Pb) Free

AZ100LVEL32NG

C2G

<Date Code>

1,3

1

Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)

Tape & Reel.

2

Date code format: “Y” or “YY” for year followed by “WW” for week on

underside of part.

3

Date code format: “Y” for year followed by “WW” for week.