Arizona Microtek, Inc.

AZP53

Low Phase Noise Sine Wave/CMOS

to LVPECL Buffer/Divider

www.azmicrotek.com

+1-480-962-5881

5

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May 2012, Rev 2.1

The LVPECL compatible output stage of the AZP53 uses a current drive topology to maximize switching speed as

illustrated below in Figure 4. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an NMOS

current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output

current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the output pin. The associated output

voltage swings match LVPECL levels when external 50

Ω resistors terminate the outputs.

Both Q and Q

¯ should always be terminated identically to avoid waveform distortion and circulating current caused by

unsymmetrical loads. This rule should be followed even if only one output is in use.

M1

M2

M3

M4

D

M5

21.1mA

21.1mA

16mA

Q

Q

50

Ω

50

Ω

21.1mA - High

5.1mA - Low

External

Circuitry

Output

Stage

Figure 4 - Typical Output Termination

The standard LVPECL loads are a pair of 50

Ω resistors connected between the outputs and V

resistors provide both the DC and the AC loads, assuming 50

Ω interconnect. If an additional supply is available within the

application, a four resistor termination configuration is possible (Figure 5).