[AK4430]

OPERATION OVERVIEW

The external clocks required to operate the AK4430 are MCLK, LRCK, and BICK. The master clock (MCLK) should be

synchronized with LRCK, but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the

delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically, and then the internal master

clock is set to the appropriate frequency (Table 1).

The AK4430 is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal operation

mode, and the analog output goes to 0V(typ). When MCLK, LRCK and BICK are input again, the AK4430 is powered

up. After exiting reset following power-up, the AK4430 is not fully operational until MCLK, LRCK and BICK are input.

LRCK

MCLK (MHz)

fs

128fs

192fs

256fs

384fs

512fs

768fs

1152fs

Sampling

Speed

32.0kHz

-

-

-

-

16.3840

24.5760

36.8640

44.1kHz

-

-

-

-

22.5792

33.8688

-

48.0kHz

-

-

-

-

24.5760

36.8640

-

Normal

32.0kHz

8.192

12.288

44.1kHz

11.2896

16.9344

48.0kHz

12.288

18.432

88.2kHz

-

-

22.5792

33.8688

-

-

-

96.0kHz

-

-

24.5760

36.8640

-

-

-

Double

176.4kHz

22.5792

33.8688

-

-

-

-

-

Quad

192.0kHz

24.5760

36.8640

-

-

-

-

-

Table 1. System Clock Example

When MCLK= 256fs/384fs, the Auto Setting Mode supports sampling rate of 32kHz~96kHz (Table 1). However, when

the sampling rate is 32kHz~48kHz, DR and S/N will degrade as compared to when MCLK= 512fs/768fs (Table 2).

MCLK

DR,S/N

256fs/384fs

101dB

512fs/768fs

104dB

Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)

The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The AK4430 supports two formats as

shown in Table 3. The serial data is MSB-first, two’s complement format and it is latched on the rising edge of BICK. It

Mode

DIF pin

SDTI Format

BICK

Figure

0

L

24bit MSB justified

≥48fs

Figure 3

1

H

Figure 4

≥48fs

Table 3. Audio Data Format

MS1196-E-01

2011/03

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