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AKD4425A Datasheet(PDF) 11 Page - Asahi Kasei Microsystems

Part # AKD4425A
Description  192kHz 24-Bit Stereo ?誇 DAC with 2Vrms Output
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Manufacturer  AKM [Asahi Kasei Microsystems]
Direct Link  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AKD4425A Datasheet(HTML) 11 Page - Asahi Kasei Microsystems

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[AK4425A]
OPERATION OVERVIEW
System Clock
The external clocks required to operate the AK4425A are MCLK, LRCK and BICK. The master clock (MCLK) should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There
are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register 00H), the sampling speed is set
by DFS0/1 (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2) When the power
applied, the AK4425A is in Auto Setting Mode. In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is
detected automatically (Table 3), and the internal master clock becomes the appropriate frequency (Table 4), it is not
necessary to set DFS0/1.
The AK4425A is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal
operation mode, and the analog output is forced to 0V(typ). When MCLK, LRCK and BICK are input again, the
AK4425A is powered up. After power-up, the AK4425A is in the power-down mode until MCLK, LRCK and BICK are
input.
DFS1
DFS0
Sampling Rate (fs)
0
0
Normal Speed Mode
8kHz~48kHz
(default)
0
1
Double Speed Mode
60kHz~96kHz
1
0
Quad Speed Mode
120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
(kHz)
MCLK (MHz)
BICK
(MHz)
DFS1
DFS0
Sampling
Speed
fs
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
64fs
0
0
32.0
-
-
8.1920
12.2880
16.3840
24.5760
36.8640
2.0480
0
0
44.1
-
-
11.2896
16.9344
22.5792
33.8688
-
2.8224
0
0
Normal
48.0
-
-
12.2880
18.4320
24.5760
36.8640
-
3.0720
0
1
88.2
11.2896
16.9344
22.5792
33.8688
-
-
-
5.6448
0
1
Double
96.0
12.2880
18.4320
24.5760
36.8640
-
-
-
6.1440
1
0
176.4
22.5792
33.8688
-
-
-
-
-
11.2896
1
0
Quad
192.0
24.5760
36.8640
-
-
-
-
-
12.2880
Table 2. System Clock Example
MCLK
Sampling Speed
1152fs
Normal (fs=32kHz only)
512fs
768fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 3. Sampling Speed(Auto Setting Mode: Default)
MS1127-E-01
2011/03
- 11 -


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