ASAHI KASEI

[AK4522]

M0020-E-02

2012/01

- 9 -

OPERATION OVERVIEW

System Clock

The master clock (MCLK) can be external clock input to the MCKI pin. CMODE is used to select either MCLK=256fs,

384fs or 512fs. The relationship between the MCLK and the desired sample rate is defined in Table 1. The LRCK clock

input must be synchronized with MCLK, however the phase is not critical. Internal timing is synchronized to LRCK upon

power-up. All external clocks must be present unless PD = “L”, otherwise excessive current may result from abnormal

operation of internal dynamic logic.

MCLK

SCLK

fs

256fs

CMODE=”L”

384fs

CMODE=”H”

512fs

CMODE=”NC”

64fs

128fs

32.0kHz

8.1920MHz

12.2880MHz

16.384MHz

2.048MHz

4.096MHz

44.1kHz

11.2896MHz

16.9344MHz

22.579MHz

2.822MHz

5.644MHz

48.0kHz

12.2880MHz

18.4320MHz

24.576MHz

3.072MHz

6.144MHz

Table 1. System Clock Example

Audio Serial Interface Format

Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. Four serial data modes selected by the DIF0

and DIF1 pins are supported as shown in Table 2. In all modes the serial data has MSB first, 2’s compliment format. The

data is clocked out on the falling edge of SCLK and latched on the rising edge. For mode 3, if SCLK is 32fs, then the least

significant bits will be truncated.

Mode

DIF1

DIF0

SDTO (ADC)

SDTI (DAC)

L/R

SCLK

0

0

0

20bit, MSB justified

16bit, LSB justified

H/L

≥ 32fs

1

0

1

20bit, MSB justified

20bit, LSB justified

H/L

≥ 40fs

2

1

0

20bit, MSB justified

20bit, MSB justified

H/L

≥ 40fs

3

1

1

IIS (I2S)

IIS (I2S)

L/H

≥ 32fs or 40fs

Table 2. Serial Data Modes

LRCK(i)

SCLK(i:64fs)

SDTO(o)

01

2

19

17

18

20

31

0

1

2

19

17

18

20

31

0

19

1

18

0

19

18

3

2

0

19

SDTI(i)

1

14

0

12

11

1

14

0

12

11

SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB

Lch Data

Rch Data

Don’t Care

Don’t Care

32

SCLK(i:32fs)

SDTO(o)

0

1

2

9

10

12

13

15

0

1

2

9

10

12

13

15

0

19

1

18

8

19

18

8

11 10

19

SDTI(i)

1

60

43

1

15

0

54

11

10

2

54

76

17

15

14 13

311

14

9

5

7

17

1

13

15

30

17

33

17

14

13

7

6

3

2

15

14

11

4

5

6

7

9

1

15

13

2

2

Figure 1. Mode 0 Timing