[AK4528]

MS0011-E-02

2012/01

- 11 -

OPERATION OVERVIEW

System Clock Input

The external clocks, which are required to AK4528, are MCLK, BICK and LRCK. MCLK should be synchronized with

LRCK but the phase is not critical. The frequency of MCLK is set by CMODE, CKS0-1 and DFS bits in serial mode, or

by CKS0-1, DFS pins in parallel mode (see Table 2 and 3). The CKS0-1 and DFS pin should be changed during the PDN

pin = “L”. The CMODE, CKS0-1 and DFS bits are changed during RSTADN = RSTDAN = “0”.

External clocks (MCLK, BICK and LRCK) should always be present whenever the AK4528 is in normal operation mode

(PDN = “H” and at least one of ADC and DAC is in normal operation mode). If these clocks are not provided, the

AK4528 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are

not present, the AK4528 should be in the power-down mode (PDN = “L” or set both ADC and DAC power down mode

by the register).

CMODE bit

CKS1 bit

CKS0 bit

MCLK

Normal Speed

(DFS bit = “0”)

MCLK

Double Speed

(DFS bit = “1”)

0

0

0

256fs

N/A

0

0

1

512fs

256fs

0

1

0

1024fs

512fs

1

0

0

384fs

N/A

1

0

1

768fs

384fs

Default

Table 1. Master Clock Frequency Select in Serial Mode

CKS1 pin

CKS0 pin

MCLK

Normal Speed

(DFS pin = “L”)

MCLK

Double Speed

(DFS pin = “H”)

L

L

256fs

N/A

L

H

512fs

256fs

H

L

384fs

N/A

H

H

1024fs

512fs

Table 2. Master Clock Frequency Select in Parallel Mode

MCLK

Normal Speed

(DFS = “0”)

fs=44.1kHz

fs=48kHz

MCLK

Double Speed

(DFS = “1”)

fs=88.2kHz

fs=96kHz

256fs

11.2896MHz

12.288MHz

N/A

N/A

N/A

512fs

22.5792MHz

24.576MHz

256fs

22.5792MHz

24.576MHz

1024fs

45.1584MHz

49.152MHz

512fs

45.1584MHz

49.152MHz

384fs

16.9344MHz

18.432MHz

N/A

N/A

N/A

768fs

33.8688MHz

36.864MHz

384fs

33.8688MHz

36.864MHz

Table 3. Master Clock Frequencies example

Note. Do not set any mode which is not described in Table1-3.