Semiconductor Group

10

HYM72V8020/30GS-50/-60

8M x 72-ECC Module

Notes:

1) All voltages are referenced to VSS.

2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.

3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.

4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less

during a fast page mode cycle ( tpc).

5) An initial pause of 100

device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS

initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume tT = 5 ns.

7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are

measured between VIH and VIL.

8) The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns (CAS, WE, OE,

addresses) maximum delay, no pulse shrinkage to the DRAM device timings. The data and RAS signals are

not buffered, which preserves the DRAMs access specification of 50ns and 60ns.

9) A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers.

10) A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers.

11) A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers.

12) A -2ns (min.) and a -5ns (max.) timing skew from the DRAM to the module resulted from the addition of line

drivers.

13) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.

14) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a

reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by

tCAC.

15) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a

reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by

tAA.

16) Either tRCH or tRRH must be satisfied for a read cycle.

17) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are

not referenced to output voltage levels.

18) Either tDZC or tDZO must be satisfied.

19) Either tCDD or tODD must be satisfied.

20) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin

will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD

(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will

contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition

of the I/O pins (at access time) is indeterminate.

21) These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-

Modify-Write cycles.