AK8181A

Nov-2011

MS1342-E-00

- 6 -

Function Table

The following table shows the inputs/outputs clock state configured through the control pins.

Table 1: Control Input Function Table

Inputs

Outputs

CLK_EN

CLK_SEL

Selected Source

Q0:Q3

Q0n:Q3n

0

0

CLK0

Disabled: Low

Disabled: High

0

1

CLK1

Disabled: Low

Disabled: High

1

0

CLK0

Enabled

Enabled

1

1

CLK1

Enabled

Enabled

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge

as shown in Figure 7. In the active mode, the state of the outputs is a function of the CLK0 and CLK1 as

described in Table 2.

CLK0, CLK1

CLK_EN

Q0n : Q3n

Q0 : Q3

Disabled

Enabled

Figure 7 CLK_EN Timing Diagram

Table 2 Clock Input Function Table

Inputs

Outputs

CLK0 or CLK1

Q0 : Q3

Q0n : Q3n

0

Low

High

1

High

Low