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AKD4122A-A Datasheet(PDF) 11 Page - Asahi Kasei Microsystems |
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AKD4122A-A Datasheet(HTML) 11 Page - Asahi Kasei Microsystems |
11 / 37 page [AKD4122A-A] (4) Setting for Output port (AK4122A PORT2) (4-1) Slave mode 1. When using DIT function of AK4114 (U13) When using X’tal (X1) and PORT8 (DIT2), nothing should be connected to PORT6 (DIR2) and PORT7 (DSP2). Set JP18 (MCLK2) to the “DIR” when MCLK is supplied to the AK4122A. When MCLK frequency is changed, the value of X’tal (X1) frequency should be changed according to MCLK frequency. JP15 SDTIO JP16 BICK2 EXT DIR JP17 LRCK2 EXT DIR JP18 MCLK2 EXT DIR • SW3 setting (See Table 11,Table 12,Table 13) Upper-side is “H” and lower-side is “L”. SW3 No. Name ON (“H”) OFF (“L”) 1 OCKS AK4114 Master Clock Output Setting Refer to Table 12 2 DIF0 3 DIF1 4 DIF2 AK4114 Audio Format Setting Refer to Table 13 Table 11. SW3 setting Mode OCKS MCKO1 X’tal fs 0 0 256fs 256fs ∼ 96kHz Default 1 1 512fs 512fs ∼ 48kHz Table 12. AK4114 MCKO1 setting AK4114 AK4122A Mode Audio I/F Format DIF2 DIF1 DIF0 IDIF1 IDIF0 0 24bit, MSB justified 1 0 0 0 0 1 24bit, MSB justified 1 0 0 0 1 Default 2 24bit, I 2S Compatible 1 0 1 1 0 3 24bit, MSB justified 1 0 0 1 1 Table 13. AK4114 Audio interface format setting * IDIF1-0 of the AK4122A is set by the register. <KM099400> 2009/03 - 11 - |
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