[AKD4392-SB]

<KM099800>

4

2009/06

The frequency of the master clock output is set by OCKS0 and OCKS1 as shown in Table 4.

OCKS1

OCKS0

MCLK Frequency

L

L

256fs @fs=88.2/96kHz

H

L

512fs @fs=32/44.1/48kHz

(Default)

H

H

128fs @fs=176.4/192kHz

SW3 setting

[SW3](PDN): Reset of AK4392. Select “H” during operation

.

External Analog Circuit

The differential output circuit and LPF is implemented on board. The differential outputs of AK4392 is buffered by non-inverted circuit(2

nd

order LPF, fc=106.4k, Q=0.698, G=+3.9dB). LPF adds differential outputs(1

for op-amp on this board that has low noise and high voltage torelance characteristics. Analog signal is output via BNC connectors on the

board. The output level is about 2.8Vrms (typ@VREF=5.0V) by BNC.

220

100u

220

AOUTL-

6.8n

680

6.8n

6

4

3

2

7

10u

0.1u

0.1u

10u

10u

LME49710NA

220

100u

220

AOUTL+

6.8n

680

6.8n

6

4

3

2

7

10u

0.1u

0.1u

10u

LME49710NA

0.1u

+

LME49710NA

0.1u

10u

100

4

3

2

1.0n

620

620

560

7

+

+

+

+

-

+

-

+

+

+

-

+

+

1.0n

Lch

-15

+15

6

Figure 2. External Analog Filter

AKD4392-SB

Filter

40kHz (Double)

80kHz (quad)

Internal Filter

-0.3dB

-1dB

External LPF

-0.12dB

-1.3dB

Total

-0.42dB

-2.3dB

This table shows typical value.

Table 5. Frequency Responses