HYS64(72)V8000GU-10

8M x 64/72 SDRAM-Module

Semiconductor Group

9

Notes:

1. The specified values are valid when addresses are changed no more than once during tck(min.)

and when No Operation commands are registered on every rising clock edge during tRC(min).

2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).

3. An initial pause of 100

µs is required after power-up, then a Precharge All Banks command must

be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can

begin.

with the AC output load circuit shown.

7. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh

commands must be given to “wake-up“the device.

8. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after

CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied

once the Self Refresh Exit command is registered.

9. Referenced to the time which the output achieves the open circuit condition, not to output voltage

levels.

1.4V

1.4V

tSETUP

tHOLD

tAC

tAC

tLZ

tOH

tHZ

CLOCK

INPUT

OUTPUT

50 pF

I/O

Z=50 Ohm

+ 1.4 V

50 Ohm

2.4 V

0.4 V

fig.1

tCH

tCL