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PC100-323-620 Datasheet(PDF) 8 Page - Siemens Semiconductor Group

Part # PC100-323-620
Description  3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
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Manufacturer  SIEMENS [Siemens Semiconductor Group]
Direct Link  http://www.siemens.com/
Logo SIEMENS - Siemens Semiconductor Group

PC100-323-620 Datasheet(HTML) 8 Page - Siemens Semiconductor Group

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HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
Semiconductor Group
8
AC Characteristics 3)4)
T
A = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
Unit
Note
-8
PC100
2-2-2
-8-3
PC100
3-2-3
-10
PC66
2-2-2
min.
max.
min.
max.
min.
max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
t
CK
10
10
10
10
10
15
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
f
CK
100
100
100
100
100
66
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
t
AC
6
6
6
7
8
9
ns
ns
4,5)
Clock High Pulse Width
t
CH
3–3
3.5
ns
6)
Clock Low Pulse Width
t
CL
3–3
3.5
ns
6)
Input Setup time
t
CS
2–2
–3–
ns
7)
Input Hold Time
t
CH
1–1
–1–
ns
7)
CKE Setup Time
(Power down mode)
t
CKSP
2.5
2.5
3
ns
8)
CKE Setup Time
(Self Refresh Exit)
t
CKSR
8–8
–8–
ns
9)
Transition time (rise and fall)
t
T
1–1
–1–
ns
Common Parameters
RAS to CAS delay
t
RCD
20
20
30
ns
Cycle Time
t
RC
70
120k
70
120k
75
120k ns
Active Command Period
t
RAS
45
45
45
ns
Precharge Time
t
RP
20
30
30
ns
Bank to Bank Delay Time
t
RRD
16
20
20
ns
CAS to CAS delay time
(same bank)
t
CCD
1–1
–1–
CLK


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