2.1MHz, High-Voltage,

600mA Mini-Buck Converter

______________________________________________________________________________________

11

ESR of the input capacitor). The total voltage ripple is

the sum of

ripple from the ESR and the capacitor discharge is

equal to 50% each. The following equations show the

ESR and capacitor requirement for a target voltage rip-

ple at the input:

where:

and:

input capacitance at lower input voltages to avoid pos-

sible undershoot below the UVLO threshold during tran-

sient loading.

Output Capacitor

The allowable output-voltage ripple and the maximum

deviation of the output voltage during step load cur-

rents determine the output capacitance and its ESR.

The output ripple comprises of

capacitor discharge) and

the output capacitor). Use low-ESR ceramic or alu-

minum electrolytic capacitors at the output. For alu-

minum electrolytic capacitors, the entire output ripple is

contributed by

culate the ESR requirement and choose the capacitor

accordingly. If using ceramic capacitors, assume the

contribution to the output ripple voltage from the ESR

and the capacitor discharge to be equal. The following

equations show the output capacitance and ESR

requirement for a specified output-voltage ripple.

where:

The allowable deviation of the output voltage during

fast transient loads also determines the output capaci-

tance and its ESR. The output capacitor supplies the

step load current until the converter responds with a

depends on the closed-loop bandwidth of the convert-

er. The device’s high switching frequency allows for a

higher closed-loop bandwidth, thus reducing

The resistive drop across the output capacitor’s ESR

and the capacitor discharge causes a voltage droop

during a step load. Use a combination of low-ESR tan-

talum and ceramic capacitors for better transient load

and ripple/noise performance. Keep the maximum out-

put-voltage deviations below the tolerable limits of the

electronics being powered. When using a ceramic

capacitor, assume an 80% and 20% contribution from

the output capacitance discharge and the ESR drop,

respectively. Use the following equations to calculate

the required ESR and capacitance value:

response time of the converter. The converter response

time depends on the control-loop bandwidth.

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching

power losses and clean stable operation. Use a multilayer

board wherever possible for better noise immunity. Refer

to the MAX16904 Evaluation Kit for recommended PCB

layout. Follow these guidelines for a good PCB layout:

1) The input capacitor (4.7μF, see the applications

schematic in the

Typical Operating Circuits) should be

placed right next to the SUP pins (pins 2 and 3 on the

TSSOP-EP package). Because the device operates at

2.1MHz switching frequency, this placement is critical

for effective decoupling of high-frequency noise from

the SUP pins.

ESR

V

I

C

It

V

OUT

ESR

STEP

OUT

STEP

RESPONSE

Q

=

=

×

Δ

Δ

ΔI

VV

V

Vf

L

V

PP

IN

OUT

OUT

IN

SW

OUT RIPPLE

−×

××

()

_

≅≅+

ΔΔ

VV

ESR

Q

ESR

V

I

C

I

Vf

ESR

PP

OUT

PP

QSW

=

=

××

−

−

Δ

Δ

Δ

Δ

8

D

V

V

OUT

IN

=

ΔI

VV

V

Vf

L

PP

IN

OUT

OUT

IN

SW

−×

××

()

ESR

V

I

I

C

ID

D

ESR

OUT

PP

IN

OUT

=

+

⎛

⎝⎜

⎞

⎠⎟

=

×−

−

Δ

Δ

2

1

(

))

ΔVf

QSW

×