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MCM63P631TQ117 Datasheet(PDF) 9 Page - Motorola, Inc |
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MCM63P631TQ117 Datasheet(HTML) 9 Page - Motorola, Inc |
9 / 16 page MCM63P631 9 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level 1.5 V . . . . . . . . . . . . . . . Input Pulse Levels 0 to 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Rise/Fall Time 1 V/ns (20 to 80%) . . . . . . . . . . . . . . . . . . . . . . . Output Timing Reference Level 1.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . Output Load See Figure 1 Unless Otherwise Noted . . . . . . . . . . . . . . READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4) 63P631–117 117 MHz 63P631–4.5 100 MHz 63P631–7 75 MHz 63P631–8 66 MHz Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Cycle Time tKHKH 8.5 — 10 — 13.3 — 15 — ns Clock High Pulse Width tKHKL 3.6 — 4 — 5.3 — 6 — ns Clock Low Pulse Width tKLKH 3.6 — 4 — 5.3 — 6 — ns Clock Access Time tKHQV — 4.5 — 4.5 — 7 — 8 ns Output Enable to Output Valid tGLQV — 4.5 — 4.5 — 5 — 5 ns Clock High to Output Active tKHQX1 0 — 0 — 0 — 0 — ns 5 Clock High to Output Change tKHQX2 1.5 — 1.5 — 1.5 — 1.5 — ns 5 Output Enable to Output Active tGLQX 0 — 0 — 0 — 0 — ns 5 Output Disable to Q High–Z tGHQZ — 5.5 — 5.5 — 7 — 8 ns 5, 6 Clock High to Q High–Z tKHQZ 1.5 5.5 1.5 5.5 2 7 2 8 ns 5, 6 Setup Times: Address ADSP, ADSC, ADV Data In Write Chip Enable tADKH tADSKH tDVKH tWVKH tEVKH 2.5 — 2.5 — 2.5 — 2.5 — ns Hold Times: Address ADSP, ADSC, ADV Data In Write Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHEX 0.5 — 0.5 — 0.5 — 0.5 — ns Sleep Mode Standby tZZS — 2 x tKHKH — 2 x tKHKH — 2 x tKHKH — 2 x tKHKH ns Sleep Mode Recovery tZZREC 2 x tKHKH — 2 x tKHKH — 2 x tKHKH — 2 x tKHKH — ns Sleep Mode High to Q High–Z tZZQZ — 15 — 15 — 15 — 15 ns NOTES: 1. Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high. 2. Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted. 3. All read and write cycle timings are referenced from K or G. 4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle. 5. This parameter is sampled and is not 100% tested. 6. Measured at ± 200 mV from steady state. OUTPUT Z0 = 50 Ω RL = 50 Ω VT = 1.5 V Figure 1. AC Test Load |
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