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MCM63P636ZP225 Datasheet(PDF) 4 Page - Motorola, Inc |
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MCM63P636ZP225 Datasheet(HTML) 4 Page - Motorola, Inc |
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4 / 27 page  MCM63P636 4 MOTOROLA FAST SRAM PBGA PIN DESCRIPTIONS Pin Locations Symbol Type Description 5D ADS Input Synchronous Address Status: Active low, used to initiate read or write state machines latch in external addresses, or deselect chip. (a) 1B, 2B, 1D, 2D, 3D, 1F, 2F, 1H, 2H, 1K, 2K, 1M, 2M, 1P, 2P, 3P, 1T, 2T (b) 8B, 9B, 7D, 8D, 9D, 8F, 9F, 8H, 9H, 8K, 9K, 8M, 9M, 7P, 8P, 9P, 8T, 9T DQx I/O Synchronous Data I/O: “x” refers to the word being read or written (I/Os a and b). 5F K Input Clock: This signal registers the address, data in, and all control signals. 6C RESET Input Asynchronous Power–On Reset: Active low at power up, resets internal state machines. 3A, 7A, 3B, 7B, 5M, 5N, 4P, 5P, 6P, 4R, 6R, 3T, 4T, 6T SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 5R, 5T SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 4A SE1 Input Synchronous Chip Enable: Active low to enable chip. 5A SE2 Input Synchronous Chip Enable: Active high to enable chip. 4B SE3 Input Synchronous Chip Enable: Active low to enable chip. 5G SK Input Data Strobe Clock: 180 degrees out–of–phase with K. Used only with data strobes. 3K STRBA Output Data Strobe: Used in reference to DQa I/Os. 3H STRBA Output Data Strobe: Used in reference to DQa I/Os. 7K STRBB Output Data Strobe: Used in reference to DQb I/Os. 7H STRBB Output Data Strobe: Used in reference to DQb I/Os. 5U TCK Input Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK must be tied to VDD or VSS. 3U TDI Input Boundary Scan Pin, Test Data In. 7U TDO Output Boundary Scan Pin, Test Data Out. 4U TMS Input Boundary Scan Pin, Test Mode Select. 6U TRST Input Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not used, TRST must be tied to VSS. 5C W Input Synchronous Write. 4D, 6D, 3E, 7E, 4F, 6F, 3G, 7G, 4H, 6H, 4K, 6K, 3L, 7L, 4M, 6M, 3N, 7N VDD Supply Core Power Supply. 3F, 7F, 3M, 7M VDDI Supply Input Power Supply. 2A, 8A, 2C, 8C, 2E, 8E, 2G, 8G, 2J, 8J, 2L, 8L, 2N, 8N, 2R, 8R, 2U, 8U VDDQ Supply I/O Power Supply. 1A, 9A, 1C, 3C, 7C, 9C, 1E, 4E, 5E, 6E, 9E, 1G, 4G, 6G, 9G, 5H, 1J, 3J, 4J, 6J, 7J, 9J, 1L, 4L, 5L, 6L, 9L, 1N, 4N, 6N, 9N, 1R, 3R, 7R, 9R, 1U, 9U VSS Supply Ground. 6A, 5B, 5K, 7T NC — No Connection: There is no connection to the chip. 6B NU/VDD — Not Usable: There is an internal connection to the chip. This pin may be left unconnected or tied to VDD. 4C, 5J NU/VSS — Not Usable: There is an internal connection to the chip. This pin may be left unconnected or tied to VSS. |
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