LXXLD50

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

2 of 11

www.unisonic.com.tw

QW-R502-474.B

MARKING INFORMATION

PACKAGE

VOLTAGE CODE

MARKING

HSOP-8

25 : 2.5V

AD: ADJ

PIN CONFIGURATION

PIN DESCRIPTION

PIN NO.

PIN NAME

DESCRIPTION

1

GND

Ground pin of the circuitry. All voltage levels are measured with respect to this pin.

2

ADJ

This pin, when grounded, sets the output voltage by the internal feedback resistors;

(V) where R1 is connected from VOUT to ADJ with Kelvin sensing and R2 is connected

from ADJ to GND. A bypass capacitor may be connected with R1in parallel to improve

load transient response. The recommended R2 and R1 are in the range of 100~10kΩ.

3

4

Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is

necessary to connect a output capacitor with this pin for closed-loop compensation and

improving transient responses.

5

Main supply input pins for power conversions. The Exposed Pad provide a very low

impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN

Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored

for Power-On Reset purpose.

6

Power input pin of the control circuitry. Connecting this pin to a +5V (recommended)

supply voltage provides the bias for the control circuitry. The voltage at this pin is

monitored for Power-On Reset purpose.

7

Power-OK signal output pin. This pin is an open-drain output used to indicate status of

output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage

is not above the VPOK threshold or the falling FB voltage is below the VPNOK

threshold, indicating the output is not OK.

8

EN

Enable control pin. Pulling and holding this pin below 0.3V shuts down the output.

When re-enabled, the IC undergoes a new soft-start cycle . Left this pin open, an