BS616UV2019

R0201-BS616UV2019

Revision

1.4

Oct.

2008

2

PIN DESCRIPTIONS

Name

Function

A0-A16 Address Input

These 17 address inputs select one of the 262,144 x 16 bit in the RAM

CE Chip Enable 1 Input

CE2 Chip Enable 2 Input

CE is active LOW and CE2 is active HIGH. Both chip enables must be active when

data read from or write to the device. If either chip enable is not active, the device is

deselected and is in standby power mode. The DQ pins will be in the high impedance

state when the device is deselected. (48B BGA ignore CE2 pin)

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impendence state when OE is inactive.

LB and UB Data Byte Control Input

Lower byte and upper byte data input/output control pins.

DQ0-DQ15 Data Input/Output

Ports

16 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

Ground

TRUTH TABLE

MODE

CE

WE

OE

LB

UB

H

X

X

X

X

X

High Z

High Z

X

L

X

X

X

X

High Z

High Z

Chip De-selected

(Power Down)

X

X

X

X

H

H

High Z

High Z

L

H

H

H

L

X

High Z

High Z

Output Disabled

L

H

H

H

X

L

High Z

High Z

L

L

H

L

High Z

Read

L

H

H

L

L

H

High Z

L

L

H

L

X

Write

L

H

L

X

L

H

X

1. 48BGA ignore CE2 condition.