8565

Preliminary

LINEAR INTEGRATED CIRCUIT

UNISONICTECHNOLOGIESCO.,LTD

9 of 13

www.unisonic.com.tw

QW-R114-004.b

FUNCTIONAL DESCRIPTION(Cont.)

4.4 Open Loop Protection / Input Under Voltage Protect (OLP)

case, most of the blocks within the IC will be shutdown. The function is implemented using comparator C3 with a

threshold of 0.8V as shown in the IC block diagram in Fig. 2.

4.5 Output Under Voltage Detection (OUV)

In the event of main interrupt or brown-out condition, the PFC system is not able to deliver the rated output power.

4.6 Over-Voltage Protection (OVP)

higher than 5.25V will immediately reduce the output duty cycle, bypassing the normal voltage loop control. This

5. Frequency Setting

The switching frequency of the PFC controller is fixed and can be set by an external resistor R5 at FREQ pin. The

R5/frequency relationship is given at the “Electrical Characteristic” section. The recommended operating frequency

133kHz typically.

6. Average Current Control

6.1 Complete Current Loop

Fig. 10 show the complete system current loop. It consists of the current loop block which averages the voltage at

internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator

C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the

inductor current. The following sections describe the functionality of each individual blocks.

L1

D1

C2

R4

R3

GATE

Gate

Driver

R

S

Q

PWM Logic

Input From

Voltage Loop

Nonlinear

Gain

Fault

4V

S2

1.1mS +/-50μA

(linear range)

Current Loop

Compensation

Current Loop

OTA2

+

-

UTC 8565

R7

R1

R2

From

Full-wave

Retifier

C3

C1

+

-

PWM

Comparator

Inductor current

voltage

proportional to

averaged

Fig. 10 Complete System Current Loop