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8565L-S08-T Datasheet(PDF) 9 Page - Unisonic Technologies |
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8565L-S08-T Datasheet(HTML) 9 Page - Unisonic Technologies |
9 / 13 page 8565 Preliminary LINEAR INTEGRATED CIRCUIT UNISONICTECHNOLOGIESCO.,LTD 9 of 13 www.unisonic.com.tw QW-R114-004.b FUNCTIONAL DESCRIPTION(Cont.) 4.4 Open Loop Protection / Input Under Voltage Protect (OLP) Whenever VSENSE voltage falls below 0.8V, or equivalently VOUT falls below 16% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected) or an insufficient input voltage VIN for normal operation. In this case, most of the blocks within the IC will be shutdown. The function is implemented using comparator C3 with a threshold of 0.8V as shown in the IC block diagram in Fig. 2. 4.5 Output Under Voltage Detection (OUV) In the event of main interrupt or brown-out condition, the PFC system is not able to deliver the rated output power. This will cause the output voltage VOUT to drop below its rated value. The IC provides an output under voltage detection that checks if VOUT is falling below 50% of its rated value. Comparator C4 as shown in the device block diagram (Fig. 2) senses the voltage at pin 1 (VSENSE) with a reference of 2.5V. If comparator C4 trips, the IC will be shut down as in OLP. The IC will be ready to restart if there is sufficient VIN to pull VOUT out of OLP. 4.6 Over-Voltage Protection (OVP) Whenever VOUT exceeds the rated value by 5%, the over-voltage protection OVP is active as shown in Fig. 7. This is implemented by sensing the voltage at pin VSENSE with respect to a reference voltage of 5.25V. A VSENSE voltage higher than 5.25V will immediately reduce the output duty cycle, bypassing the normal voltage loop control. This results in a lower input power to reduce the output voltage VOUT. 5. Frequency Setting The switching frequency of the PFC controller is fixed and can be set by an external resistor R5 at FREQ pin. The pin voltage VFREQ is typically 2.5V. The corresponding capacitor for the oscillator is integrated in the device and the R5/frequency relationship is given at the “Electrical Characteristic” section. The recommended operating frequency range is from 50kHz to 250kHz. As an example, a R5 of 33kΩ at pin FREQ will set a switching frequency FSW of 133kHz typically. 6. Average Current Control 6.1 Complete Current Loop Fig. 10 show the complete system current loop. It consists of the current loop block which averages the voltage at pin ISENSE, resulted from the inductor current flowing across R1. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks. L1 D1 C2 R4 R3 VOUT GATE Gate Driver R S Q PWM Logic Input From Voltage Loop Nonlinear Gain Fault 4V S2 1.1mS +/-50μA (linear range) Current Loop Compensation Current Loop OTA2 + - UTC 8565 R7 R1 R2 From Full-wave Retifier ISENSE ICOMP C3 C1 + - PWM Comparator Inductor current voltage proportional to averaged Fig. 10 Complete System Current Loop |
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