MCM6709BR

3

MOTOROLA FAST SRAM

Parameter

Symbol

Max

Unit

Address Input Capacitance

Cin

5

pF

Control Pin Input Capacitance(E, G, W)

Cin

6

pF

Input/Output Capacitance

CI/O

6

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . . . .

Input Pulse Levels

0 to 3.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time

2 ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . .

Output Load

See Figure 1a

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCM6709BR–6

MCM6709BR–7

MCM6709BR–8

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

6

—

7

—

8

—

ns

3

Address Access Time

tAVQV

—

6

—

7

—

8

ns

Chip Enable Access Time

tELQV

—

6

—

7

—

8

ns

Output Enable Access Time

tGLQV

—

4

—

4

—

4

ns

Output Hold from Address Change

tAXQX

3

—

3

—

3

—

ns

Chip Enable Low to Output Active

tELQX

3

—

3

—

3

—

ns

4, 5, 6

Output Enable Low to Output Active

tGLQX

0

—

0

—

0

—

ns

4, 5, 6

Chip Enable High to Output High–Z

tEHQZ

—

3

—

3.5

—

3.5

ns

4, 5, 6

Output Enable High to Output High–Z

tGHQZ

—

3

—

3.5

—

3.5

ns

4, 5, 6

NOTES:

1. W is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus

contention conditions during read and write cycles.

3. All read cycle timings are referenced from the last valid address to the first transitioning address.

4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given

device and from device to device.

5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.

6. This parameter is sampled and not 100% tested.

OUTPUT

Z0 = 50 Ω

RL = 50 Ω

VL = 1.5 V

(a)

(b)

5 pF

+5 V

OUTPUT

255

Ω

480

Ω

The table of timing values shows either a

minimum or a maximum limit for each param-

eter. Input requirements are specified from

the external system point of view. Thus, ad-

dress setup time is shown as a minimum

since the system must supply at least that

much time. On the other hand, responses

from the memory are specified from the de-

vice point of view. Thus, the access time is

shown as a maximum since the device never

provides data later than that time.

TIMING LIMITS

Figure 1. AC Test Loads