ADF4196

Data Sheet

Rev. B | Page 4 of 28

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SW1, SW2, AND SW3

On Resistance

SW1 and SW2

65

Ω

SW3

75

Ω

NOISE CHARACTERISTICS

Output

900 MHz2

−108

dBc/Hz

At 5 kHz offset and 26 MHz PFD frequency

1800 MHz3

−102

dBc/Hz

At 5 kHz offset and 13 MHz PFD frequency

Phase Noise

Normalized Phase Noise Floor

−216

dBc/Hz

At VCO output with dither off, PLL loop

bandwidth = 500 kHz

−110

dBc/Hz

Measured at 10 kHz offset, normalized to 1 GHz

1

Choose a prescaler value that ensures that the frequency on the RF input is less than the maximum allowable prescaler frequency (750 MHz).

2

3

4

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider

5

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency,

ADIsimPLL™.

TIMING CHARACTERISTICS

Table 2.

Parameter

Limit

Description

10 ns min

LE setup time

10 ns min

DATA to CLK setup time

10 ns min

DATA to CLK hold time

15 ns min

CLK high duration

15 ns min

CLK low duration

10 ns min

CLK to LE setup time

15 ns min

LE pulse width

Timing Diagram

CLK

DATA

DB23

(MSB)

DB22

DB1 (LSB)

(CONTROL BIT C2)

DB2 (LSB)

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

LE

LE

Figure 2. Timing Diagram