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ADF4196BCPZ Datasheet(PDF) 4 Page - Analog Devices |
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ADF4196BCPZ Datasheet(HTML) 4 Page - Analog Devices |
4 / 28 page ADF4196 Data Sheet Rev. B | Page 4 of 28 Parameter Min Typ Max Unit Test Conditions/Comments SW1, SW2, AND SW3 On Resistance SW1 and SW2 65 Ω SW3 75 Ω NOISE CHARACTERISTICS Output 900 MHz2 −108 dBc/Hz At 5 kHz offset and 26 MHz PFD frequency 1800 MHz3 −102 dBc/Hz At 5 kHz offset and 13 MHz PFD frequency Phase Noise Normalized Phase Noise Floor (PNSYNTH)4 −216 dBc/Hz At VCO output with dither off, PLL loop bandwidth = 500 kHz Normalized 1/f Noise (PN1_f)5 −110 dBc/Hz Measured at 10 kHz offset, normalized to 1 GHz 1 Choose a prescaler value that ensures that the frequency on the RF input is less than the maximum allowable prescaler frequency (750 MHz). 2 fREFIN = 26 MHz; fSTEP = 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz. 3 fREFIN = 13 MHz; fSTEP = 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz. 4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(fPFD). PNSYNTH = PNTOT − 10 log(fPFD) − 20 log(N). 5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL™. TIMING CHARACTERISTICS AVDD = DVDD1, DVDD2, DVDD3 = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; AGND1, AGND2 = DGND1, DGND2, DGND3 = 0 V; RSET = 2.4 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature = −40°C to +85°C. Table 2. Parameter Limit Description t1 10 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 15 ns min CLK high duration t5 15 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 15 ns min LE pulse width Timing Diagram CLK DATA DB23 (MSB) DB22 DB1 (LSB) (CONTROL BIT C2) DB2 (LSB) (CONTROL BIT C3) DB0 (LSB) (CONTROL BIT C1) LE LE t2 t4 t5 t3 t7 t6 t1 Figure 2. Timing Diagram |
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