ADIS16485

Data Sheet

Rev. 0 | Page 10 of 28

SPI COMMUNICATION

The SPI port supports full duplex communication, as shown in

Figure 17, which enables external processors to write to DIN

while reading DOUT, when the previous command was a read

request. Figure 17 provides a guideline for the bit coding on

both DIN and DOUT.

DEVICE CONFIGURATION

The SPI provides write access to the control registers, one byte

at a time, using the bit assignments shown in Figure 17. Each

register has 16 bits, where Bits[7:0] represent the lower address

(listed in Table 9) and Bits[15:8] represent the upper address.

Write to the lower byte of a register first, followed by a write to

its upper byte. The only register that changes with a single write to

its lower byte is the PAGE_ID register. For a write command,

the first bit in the DIN sequence is set to 1. Address Bits[A6:A0]

represent the target address, and Data Command Bits[DC7:DC0]

represent the data being written to the location. Figure 13 provides

an example of writing 0x03 to Address 0x00 (PAGE_ID [7:0]),

using DIN = 0x8003. This write command activates the control

page for SPI access.

SCLK

CS

DIN

DIN = 1000 0000 0000 0011 = 0x8003, WRITES 0x03 TO ADDRESS 0x00

Figure 13. SPI Sequence for Activating the Control Page (DIN = 0x8003)

Dual Memory Structure

Writing configuration data to a control register updates its SRAM

contents, which are volatile. After optimizing each relevant control

register setting in a system, use the manual flash update command,

which is located in GLOB_CMD[3] on Page 3 of the register map.

Activate the manual flash update command by turning to Page 3

(DIN = 0x8003) and setting GLOB_CMD[3] = 1 (DIN = 0x8208,

then DIN = 0x8300). Make sure that the power supply is within

specification for the entire 375 ms processing time for a flash

memory update. Table 9 provides a memory map for all of the user

registers, which includes a column of flash backup information. A

yes in this column indicates that a register has a mirror location

in flash and, when backed up properly, automatically restores

itself during startup or after a reset. Figure 14 provides a diagram of

the dual memory structure used to manage operation and store

critical user settings.

NONVOLATILE

FLASH MEMORY

(NO SPI ACCESS)

MANUAL

FLASH

BACKUP

START-UP

RESET

VOLATILE

SRAM

SPI ACCESS

Figure 14. SRAM and Flash Memory Diagram

READING SENSOR DATA

The ADIS16485 automatically starts up and activates Page 0 for

data register access. Write 0x00 to the PAGE_ID register (DIN =

0x8000) to activate Page 0 for data access after accessing any other

page. A single register read requires two 16-bit SPI cycles. The

first cycle requests the contents of a register using the bit assignments

in Figure 17, and then the register contents follow DOUT during

the second sequence. The first bit in a DIN command is zero,

followed by either the upper or the lower address for the register.

The last eight bits are don’t care, but the SPI requires the full set

of 16 SCLKs to receive the request. Figure 15 includes two register

reads in succession, which starts with DIN = 0x1A00 to request

the contents of the Z_GYRO_OUT register and follows with

0x1800 to request the contents of the Z_GYRO_LOW register.

DIN

DOUT

0x1A00

0x1800

NEXT

ADDRESS

Z_GYRO_OUT

Z_GYRO_LOW

Figure 15. SPI Read Example

Figure 16 provides an example of the four SPI signals when reading

PROD_ID in a repeating pattern. This is a good pattern to use

for troubleshooting the SPI interface setup and communications

because the contents of PROD_ID are predefined and stable.

SCLK

CS

DIN

DOUT

DOUT = 0100 0000 0110 0101 = 0x4065 = 16,485 (PROD_ID)

DIN = 0111 1110 0000 0000 = 0x7E00

Figure 16. SPI Read Example, Second 16-Bit Sequence

R/W

R/W

A6

A5

A4

A3

A2

A1

A0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

CS

SCLK

DIN

DOUT

A6

A5

D13

D14

D15

NOTES

1.

DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.

2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE

FOR OTHER DEVICES.

Figure 17. SPI Communication Bit Sequence