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ADL5202ACPZ-R7 Datasheet(PDF) 7 Page - Analog Devices |
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ADL5202ACPZ-R7 Datasheet(HTML) 7 Page - Analog Devices |
7 / 32 page Data Sheet ADL5202 Rev. 0 | Page 7 of 32 Pin No. Mnemonic Description 15 VINB− Channel B Negative Input. 16 VINB+ Channel B Positive Input. 17 PWUPB Channel B Power-Up. A logic high (1.4 V ≤ PWUPB ≤ 3.3 V) enables Channel B. 19, 21 VOUTB− Channel B Negative Output. 20, 22 VOUTB+ Channel B Positive Output. 23, 24, 25, 26, 27, 28 VPOS Positive Power Supply. 29, 31 VOUTA+ Channel A Positive Output. 30, 32 VOUTA− Channel A Negative Output. 34 PWUPA Channel A Power-Up. A logic high (1.4 V ≤ PWUPA ≤ 3.3 V) enables Channel A. 35 VINA+ Channel A Positive Input. 36 VINA− Channel A Negative Input. 37 LATCHA Channel A Latch. A logic low (0 V ≤ LATCHA ≤ 0.8 V) allows gain changes on Channel A. A logic high (1.4 V ≤ LATCHA ≤ 3.3 V) prevents gain changes on Channel A. 38 UPDN_DAT_A/A0 Data Pin for Channel A Up/Down Function (UPDN_DAT_A). Bit 0 for Channel A Parallel Gain Control Interface (A0). 39 UPDN_CLK_A/A1 Clock Interface for Channel A Up/Down Function (UPDN_CLK_A). Bit 1 for Channel A Parallel Gain Control Interface (A1). 40 FA_A/A2 Fast Attack (FA_A). In serial mode, a logic high (1.4 V ≤ FA_A ≤ 3.3 V) attenuates Channel A according to FA setting in the SPI word. Bit 2 for Channel A Parallel Gain Control Interface (A2). |
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