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ADM1075-1ACPZ Datasheet(PDF) 9 Page - Analog Devices

Part # ADM1075-1ACPZ
Description  ??8 V Hot Swap Controller and Digital
Download  52 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADM1075-1ACPZ Datasheet(HTML) 9 Page - Analog Devices

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Data Sheet
ADM1075
Rev. A | Page 9 of 52
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ADR PIN
See Table 6
Address Set to 00
0
0.8
V
Connect to VEE
Input Current for Address 00
−40
−22
μA
VADR = 0 V to 0.8 V
Address Set to 01
135
150
165
Resistor to VEE
Address Set to 10
−1
+1
μA
No connect state; maximum leakage current allowed
Address Set to 11
2.1
V
Connect to VCAP
Input Current for Address 11
3
10
μA
VADR = 2.0 V to VCAP; must not exceed the maximum
allowable current draw from VCAP
SERIAL BUS DIGITAL INPUTS (SDAI/SDAO, SCL)
Input High Voltage, VIH
1.1
V
Input Low Voltage, VIL
0.8
V
Output Low Voltage, VOL
0.4
V
IOL = 4 mA, SDAO only
Input Leakage, ILEAK-PIN
−10
+10
μA
−5
+5
μA
Device is not powered
Nominal Bus Voltage, VDD
2.7
5.5
V
3 V to 5 V ±10%
Capacitive Load per Bus Segment, CBUS
400
pF
Capacitance for SDAI, SDAO, or SCL Pin, CPIN
5
pF
Input Glitch Filter, tSP
0
50
ns
SERIAL BUS TIMING
Table 2.
Parameter
Description
Min
Typ
Max
Unit
Test Conditions/Comments
fSCLK
Clock frequency
400
kHz
tBUF
Bus free time
1.3
μs
tHD;STA
Start hold time
0.6
μs
tSU;STA
Start setup time
0.6
μs
tSU;STO
Stop setup time
0.6
μs
tHD;DAT
SDA1 hold time
300
900
ns
tSU;DAT
SDA1 setup time
100
ns
tLOW
SCL low time
1.3
μs
tHIGH
SCL high time
0.6
μs
tR2
SCL, SDA1 rise time
20
300
ns
tF
SCL, SDA1 fall time
20
300
ns
tOF
SCL, SDA1 output fall time
20 + 0.1 × CBUS
250
ns
1 SDAI and SDAO tied together.
2 tR = (VIL(MAX) – 0.15) to (VIH3V3 + 0.15) and tF = 0.9 VDD to (VIL(MAX) – 0.15); where VIH3V3 = 2.1 V, and VDD = 3.3 V.
tLOW
tBUF
tHD;DAT
tSU;DAT
tSU;STA
tHD;STA
tHIGH
tR
tF
tSU;STO
P
S
S
P
VIH
VIL
VIH
VIL
SCL
SDA
Figure 2. Serial Bus Timing Diagram


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