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ADSP-BF609 Datasheet(PDF) 3 Page - Analog Devices

Part # ADSP-BF609
Description  Blackfin Dual Core
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF609 Datasheet(HTML) 3 Page - Analog Devices

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Preliminary Technical Data
Rev. PrD
|
Page 3 of 44
|
March 2012
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
GENERAL DESCRIPTION
The ADSP-BF609 processor is a member of the Blackfin
family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
The processor offers performance up to 500 MHz, as well as low
static power consumption. Produced with a low-power and low-
voltage design methodology, they provide world-class power
management and performance.
By integrating a rich set of industry-leading system peripherals
and memory (shown in Table 1), Blackfin processors are the
platform of choice for next-generation applications that require
RISC-like programmability, multimedia support, and leading-
edge signal processing in one integrated package. These applica-
tions span a wide array of markets, from automotive systems to
embedded industrial, instrumentation and power/motor con-
trol applications.
BLACKFIN PROCESSOR CORE
As shown in Figure 1, the processor integrates two Blackfin pro-
cessor cores. Each core, shown in Figure 2, contains two 16-bit
multipliers, two 40-bit accumulators, two 40-bit ALUs, four
video ALUs, and a 40-bit shifter. The computation units process
8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
Table 1. Processor Comparison
Processor Feature
Up/Down/Rotary Counters
1
Timer/Counters with PWM
8
3-Phase PWM Units (4-pair)
2
SPORTs
3
SPIs
2
USB OTG
1
Parallel Peripheral Interface
3
Removable Storage Interface
1
CAN
1
TWI
2
UART
2
ADC Control Module (ACM)
1
Link Ports
4
Ethernet MAC (IEEE 1588)
2
Pixel Compositor (PIXC)
No
1
1
Pipelined Vision Processor
(PVP)
1
No
VGA
HD
GPIOs
112
L1 Instruction SRAM
64K
L1 Instruction SRAM/Cache
16K
L1 Data SRAM
32K
L1 Data SRAM/Cache
32K
L1 Scratchpad
4K
L2 Data SRAM
128K
256K
L2 Boot ROM
32K
Maximum Speed Grade (MHz)
2
400
500
Maximum SYSCLK (MHz)
250
Package Options
349-Ball CSP_BGA
1 VGA is 640 x 480 pixels per frame, 30 frames per second. HD is 1280 x 960 pixels
per frame, 30 frames per second.
2 Maximum speed grade is not available with every possible SYSCLK selection.
Table 1. Processor Comparison (Continued)
Processor Feature


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