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SAB88C166W-5M Datasheet(PDF) 9 Page - Siemens Semiconductor Group |
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SAB88C166W-5M Datasheet(HTML) 9 Page - Siemens Semiconductor Group |
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9 / 58 page  SAB 88C166(W) Semiconductor Group 8 Memory Organization The memory space of the SAB 88C166(W) is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 256 KBytes. Address space expansion to 16 MBytes is provided for future versions. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. 1 KByte of on-chip RAM is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs). 512 bytes of the address space are reserved for the Special Function Register area. SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. 98 SFRs are currently implemented. Unused SFR addresses are reserved for future members of the SAB 80C166 family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 256 KBytes of external RAM and/or ROM can be connected to the microcontroller. Flash Memory Overview The SAB 88C166(W) provides 32 KBytes of electrically erasable and reprogrammable non-volatile Flash EPROM on-chip for code or constant data, which can be mapped to either segment 0 (0’0000H to 0’7FFFH) or segment 1 (1’0000H to 1’7FFFH) during the initialization phase. A separate Flash Control Register (FCR) has been implemented to control Flash operations like programming or erasure. For programming or erasing an external 12 V programming voltage must be applied to the VPP/EBC1 pin. The Flash memory is organized in 8 K x 32 bits, which allows even double-word instructions to be fetched in just one machine cycle. The entire Flash memory is divided into four blocks with different sizes (12/12/6/2 KByte). This allows to erase each block separately, when only parts of the Flash memory need to be reprogrammed. Word or double word programming typically takes 100 µs, block erasing typically takes 1 s (@ 20 MHz CPU clock). The Flash memory features a typical endurance of 100 erasing/programming cycles. Erased Flash memory cells contain all ‘1’s, as known from standard EPROMs. The Flash memory can be programmed both in an appropriate programming board and in the target system, which provides a lot of flexibility. The SAB 88C166(W)’s on-chip bootstrap loader may be used to load and start the programming code. To save the customer’s know-how, a Flash memory protection option is provided in the SAB 88C166(W). If this was activated once, Flash memory contents cannot be read from any location outside the Flash memory itself. |
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