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Q67000-A5186 Datasheet(PDF) 1 Page - Siemens Semiconductor Group |
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Q67000-A5186 Datasheet(HTML) 1 Page - Siemens Semiconductor Group |
1 / 23 page Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder CMOS IC P-DIP-14-3 P-DSO-20-1 Features q Single-chip receiver for PDC data, broadcast either – in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or – in dedicated line no. 16 of the vertical blanking interval (VPS) q Reception of Unified Date and Time (UDT) broadcast in BDSP 8/30/1 q Low external components count q On-chip data and sync slicer q I2C-Bus interface for communication with external microcontroller q Selection of PDC/VPS operating mode software controlled by I2C-Bus register q Pin and software compatible to VPS Decoder SDA 5642 q Supply voltage: 5 V ± 10 % q Video input signal level: 0.7 Vpp to 1.4 Vpp q Technology: CMOS q Package: P-DIP-14-3 and P-DSO-20-1 q Operating temperature range: 0 to 70 °C Semiconductor Group 21 12.94 SDA 5648 SDA 5648X Functional Description The CMOS circuit SDA 5648 is intended for use in video cassette recorders to retrieve control data of the PDC system from the data lines broadcast during the vertical blanking interval of a standard video signal. The SDA 5648 is devised to handle PDC data transported either in Broadcast Data Service Packet (BDSP) 8/30 format 2 (bytes no. 13 through 25) of CCIR teletext system B or in the dedicated data line no. 16 in the case of VPS. Furthermore it is able to receive the Unified Date and Time (UDT) information transmitted in bytes no. 15 through 21 of packet 8/30 format 1. Type Ordering Code Package SDA 5648 Q67000-A5186 P-DIP-14-3 SDA 5648X Q67006-A5198 P-DSO-20-1 Tape & Reel |
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