Decoder for Program Delivery

Control and Video Program System

PDC / VPS Decoder

CMOS IC

P-DIP-14-3

P-DSO-20-1

Features

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Single-chip receiver for PDC data, broadcast either

– in Broadcast Data Service Packet (BDSP) 8/30/2

according to CCIR teletext system B, or

– in dedicated line no. 16 of the vertical blanking interval

(VPS)

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Reception of Unified Date and Time (UDT) broadcast in

BDSP 8/30/1

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Low external components count

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On-chip data and sync slicer

microcontroller

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Selection of PDC/VPS operating mode software controlled

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Pin and software compatible to VPS Decoder SDA 5642

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Supply voltage: 5 V

± 10 %

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Video input signal level: 0.7 Vpp to 1.4 Vpp

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Technology: CMOS

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Package: P-DIP-14-3 and P-DSO-20-1

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Operating temperature range: 0 to 70

°C

Semiconductor Group

21

12.94

SDA 5648

SDA 5648X

Functional Description

The CMOS circuit SDA 5648 is intended for use in video cassette recorders to retrieve control data

of the PDC system from the data lines broadcast during the vertical blanking interval of a standard

video signal.

The SDA 5648 is devised to handle PDC data transported either in Broadcast Data Service Packet

(BDSP) 8/30 format 2 (bytes no. 13 through 25) of CCIR teletext system B or in the dedicated data

line no. 16 in the case of VPS.

Furthermore it is able to receive the Unified Date and Time (UDT) information transmitted in bytes

no. 15 through 21 of packet 8/30 format 1.

Type

Ordering Code

Package

SDA 5648

Q67000-A5186

P-DIP-14-3

SDA 5648X

Q67006-A5198

P-DSO-20-1 Tape & Reel