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Q67100-H3262 Datasheet(PDF) 8 Page - Siemens Semiconductor Group |
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Q67100-H3262 Datasheet(HTML) 8 Page - Siemens Semiconductor Group |
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8 / 10 page  SDE 2526 Semiconductor Group 89 Figure 2 Timing Conditions for the I2C Bus (high-speed mode) * Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL. Parameter Symbol Limit Values Unit min. max. Minimum time the bus must be free before a new transmission can start tBUF 4.7 µs Start condition hold time tHD;STA 4.0 µs Clock low period tLOW 4.7 µs Clock high period tHIGH 4.0 µs Start condition set-up time, only valid for repeated start code tSU;STA 4.7 µs Data set-up time tSU;DAT 250 ns Rise time of both the SDA- and SCL-line tR 1 µs Fall time of both the SDA- and SCL-line tF 300 ns Stop condition set-up time tSU;STO 4.7 µs Hold time data tHD;DAT 0*) |
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