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MCM67A618FN10 Datasheet(PDF) 4 Page - Motorola, Inc |
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MCM67A618FN10 Datasheet(HTML) 4 Page - Motorola, Inc |
4 / 12 page MCM67A618 4 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level 1.5 V . . . . . . . . . . . . . . . Input Pulse Levels 0 to 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Rise/Fall Time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Timing Reference Level 1.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . Output Load Figure 1 Unless Otherwise Noted . . . . . . . . . . . . . . . . . . ASYNCHRONOUS READ CYCLE TIMING (See Notes 1 and 2) MCM67A618–10 MCM67A618–12 MCM67A618–15 Parameter Symbol Min Max Min Max Min Max Unit Notes Read Cycle Times tAVAV 10 — 12 — 15 — ns 3 Access Times: Address Valid to Output Valid E Low to Output Valid Output Enable Low to Output Valid tAVQV tELQV tGLQV — — — 10 10 5 — — — 12 12 6 — — — 15 15 7 ns 4 Output Hold from Address Change tAXQX 4 — 4 — 4 — ns Output Buffer Control: E Low to Output Active G Low to Output Active E High to Output High–Z G High to Output High–Z tELQX tGLQX tEHQZ tGHQZ 3 1 2 2 — — 5 5 3 1 2 2 — — 6 6 3 1 2 2 — — 7 7 ns 5 Power Up Time tELICCA 0 — 0 — 0 — ns NOTES: 1. AL and DL are equal to VIH for all asynchronous cycles. 2. Both Write Enable signals (LW, UW) are equal to VIH for all read cycles. 3. All read cycle timing is referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tEHQZ is less than tELQX and tGHQZ is less than tGLQX for a given device. AC TEST LOADS Figure 1A Figure 1B 5 pF + 5 V OUTPUT 480 Ω 255 Ω OUTPUT Z0 = 50 Ω RL = 50 Ω VL = 1.5 V |
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