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Monolithic CMOS Analog Multiplexers
6
Switching Time Test Circuits (continued)
Figure 2a. Enable Switching Time
Figure 2b. Enable Switching Time
Figure 3. Break-Before-Make
Figure 4. Timing Diagrams for Figures 1, 2, and 3
-5V
S1
A1
A2
A0
EN
A3
+15V
V+
V-
-15V
DG506A
GND
SWITCH
OUTPUT
VO
1kΩ
D
50Ω
LOGIC
INPUT
S2 THRU S16
35pF
-5V
S1b
A1
A2
A0
EN
+15V
V+
V-
-15V
DG507A
GND
SWITCH
OUTPUT
VO
1kΩ
35pF
Db
50Ω
LOGIC
INPUT
S1a THRU S4a, Da,
S2b, S3b, S4b
+2.4V
VS = +5V
ALL S AND Da
A0 A1 A2 A3
EN
+15V
V+
V-
-15V
DG506A
DG507A
GND
SWITCH
OUTPUT
VO
1kΩ
Db, D
50Ω
LOGIC
INPUT
35pF
LOGIC INPUT
tr < 20ns
ti < 20ns
SWITCH OUTPUT
VO
(SEE FIGURE 1)
TRANSITION
TIME
SWITCH OUTPUT
VO
(SEE FIGURE 2)
ENABLE t(ON)/t(OFF)
TIME
SWITCH OUTPUT
VO
(SEE FIGURE 3)
3V
50%
0
tON (En)
0.1 VO
0
0.9 VO
VO
VS
VS
50%
0V
S8 ON
toff (En)
VS1
0.8 VS1
0.8 VS8
VS8
ttransition
S1 ON
ttransition
0
OPEN TIME
BREAK-BEFORE-MAKE
INTERVAL
tOPEN