MCM67A618B

8

MOTOROLA FAST SRAM

MCM67A618B–10

MCM67A618B–12

MCM67A618B–15

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Times

tAVAV

10

—

12

—

15

—

ns

3

Access Times:

Address Valid to Output Valid

E Low to Output Valid

AL High to Output Valid

Output Enable Low to Output Valid

tAVQV

tELQV

tALHQV

tGLQV

—

—

—

—

10

10

10

5

—

—

—

—

12

12

12

6

—

—

—

—

15

15

15

7

ns

3

4

Setup Times:

Address Valid to AL Low

E Valid to AL Low

Address Valid to AL High

E Valid to AL High

tAVALL

tEVALL

tAVALH

tEVALH

2

2

0

0

—

—

—

—

2

2

0

0

—

—

—

—

2

2

0

0

—

—

—

—

ns

4

4

Hold Times:

AL Low to Address Invalid

AL Low to E Invalid

tALLAX

tALLEX

2

2

—

—

2

2

—

—

3

3

—

—

ns

4

Output Hold:

Address Invalid to Output Invalid

AL High to Output Invalid

tAXQX

tALHQX1

4

4

—

—

4

4

—

—

4

4

—

—

ns

Address Latch Pulse Width

tALHALL

5

—

5

—

5

—

ns

Output Buffer Control:

E Low to Output Active

G Low to Output Active

AL High to Output Active

E High to Output High–Z

AL High to Output High–Z

G High to Output High–Z

tELQX

tGLQX

tALHQX2

tEHQZ

tALHQZ

tGHQZ

3

1

3

2

2

2

—

—

—

5

5

5

3

1

3

2

2

2

—

—

—

6

6

6

3

1

3

2

2

2

—

—

—

9

9

7

ns

5

NOTES:

1. Both Write Enable Signals (LW, UW) are equal to VIH for all read cycles.

2. All read cycle timing is referenced from the last valid address to the first transitioning address.

3. Addresses valid prior to or coincident with E going low.

4. All latched inputs must meet the specified setup and hold times with stable logic levels for ALL falling edges of address latch (AL) and data

latch (DL).

5. Transition is measured

± 500 mV from steady–state voltage with output load of Figure 1b. This parameter is sampled and not 100% tested.

At any given voltage and temperature, tEHQZ is less than tELQX and tALHQZ is less than tALHQX2 and tGHQZ is less than tGLQX for

a given device.