MCM67D709

6

MOTOROLA FAST SRAM

Processor Frequency

60 MHz

50 MHz

MCM67D709–16

MCM67D709–20

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Write Cycle Times

tKHKH

16

—

20

—

ns

1, 2

Clock Low Pulse Width

tKLKH

5

—

5

—

ns

Clock High Pulse Width

tKHKL

7

—

7

—

ns

Clock High to Output High–Z (W = VIL and

SIE = PIE = VIH)

tKHQZ

—

8

—

8

ns

3, 4

Setup Times:

A

W

PIE

SIE

SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP

tAVKL

tWLKH

tPIEVKH

tSIEVKH

tDVKH

2

2

2

2

2

—

2

2

2

2

2

—

ns

Hold Times:

A

W

PIE

SIE

SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP

tKLAX

tKHWX

tKHPIEX

tKHSIEX

tKHDX

2

2

2

2

2

—

2

2

2

2

2

—

ns

Write with Streaming (PIE = SOE = VIL or

SIE = POE = VIL) Clock High to Output Valid

tKHQV

—

5

—

7

ns

5

Output Enable High to Q High–Z

tPOEHQZ

tSOEHQZ

0

6

0

8

ns

6

Output Hold from Output Enable High

tPOEHQX

tSOEHQX

2

—

5

—

ns

6

Output Enable Low to Q Active

tPOELQX

tSOELQX

0

—

0

—

ns

6

Output Enable Low to Output Valid

tPOELQV

tSOELQV

—

5

—

6

ns

NOTES:

1. A write is performed with W = VIL for the specified setup and hold times and either PIE = VIL or SIE = VIL. If both PIE = VIL and SIE = VIL or

PIE = VIH and SIE = VIH, then this is treated like a NOP and no write is performed.

2. All write cycle timings are referenced from K.

3. K must be at a high level for the outputs to transition.

4. Transition is measured

± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.

5. A write with streaming is defined as a write cycle which writes data from one data bus to the array and outputs the same data onto the

other data bus.

6. Transition is measured

± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.

At any given voltage and temperature, tPOEHQZ is less than tPOELQX for a given device, and tSOEHQZ is less than tSOELQX for

a given device.