bq3055

SLUSA91A

– OCTOBER 2010 – REVISED JANUARY 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGE

PACKAGE

PART

DESIGNATOR

MARKING

PACKAGE

TAPE AND

NUMBER

–40°C to 85°C

bq3055

TSSOP-30

DBT

bq3055

bq3055DBT

bq3055DBTR

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of the document, or see the TI

website at www.ti.com.

(2)

A single tube quantity is 50 units.

(3)

A single reel quantity is 2000 units.

THERMAL INFORMATION

bq3055

TSSOP

UNITS

30 PINS

73.1

17.5

34.5

°C/W

0.3

30.3

n/a

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-board characterization parameter,

from the simulation data for obtaining

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

2

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