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BQ24156AYFFT Datasheet(PDF) 3 Page - Texas Instruments

Part # BQ24156AYFFT
Description  Fully Integrated Switch-Mode One-Cell Li-Ion Charger
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

BQ24156AYFFT Datasheet(HTML) 3 Page - Texas Instruments

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B1
C1
D1
SW
PMID
PGND
B2
C2
D2
SW
PMID
PGND
B3
C3
D3
SW
PMID
PGND
B4
C4
D4
STAT
SDA
OTG
A1
VBUS
A2
VBUS
A3
BOOT
A4
SCL
E1
CSIN
E2
CD
E3
VREF
E4
CSOUT
B1
C1
D1
SW
PMID
PGND
B2
C2
D2
SW
PMID
PGND
B3
C3
D3
SW
PMID
PGND
B4
C4
D4
STAT
SDA
SLRST
A1
VBUS
A2
VBUS
A3
BOOT
A4
SCL
E1
CSIN
E2
CD
E3
VREF
E4
CSOUT
bq24153A/8
(Top View)
bq24156A/9
(Top View)
bq24153A, bq24156A
bq24158, bq24159
www.ti.com
SLUSAB0A
– OCTOBER 2010 – REVISED FEBRUARY 2012
PIN LAYOUT (20-Bump YFF Package)
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1
μF) to PGND if
CSOUT
E4
I
there are long inductive leads to battery.
Charger input voltage. Bypass it with a 1-
μF ceramic capacitor from VBUS to PGND. It also provides power
VBUS
A1, A2
I/O
to the load during boost mode (bq24153A/8 only) .
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of
PMID
B1, B2, B3
I/O
3.3-
μF capacitor from PMID to PGND.
SW
C1, C2, C3
O
Internal switch to output inductor connection.
Bootstrap capacitor connection for the high-side FET gate driver. Connect a 10-nF ceramic capacitor (voltage
BOOT
A3
I/O
rating
≥ 10 V) from BOOT pin to SW pin.
PGND
D1, D2, D3
Power ground
Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-
μF ceramic
CSIN
E1
I
capacitor to PGND is required.
SCL
A4
I
I2C interface clock. Connect a 10-k
Ω pullup resistor to 1.8V rail (VAUX= VCC_HOST)
SDA
B4
I/O
I2C interface data. Connect a 10-k
Ω pullup resistor to 1.8V rail (VAUX= VCC_HOST)
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-
μs
STAT
C4
O
pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to
drive a LED or communicate with a host processor.
Internal bias regulator voltage. Connect a 1
µF ceramic capacitor from this output to PGND. External load on
VREF
E3
O
VREF is not recommended.
Charge disable control pin. CD=0, charge is enabled. CD=1, charge is disabled and VBUS pin is high
CD
E2
I
impedance to GND. In 15min mode, Setting CD=1 resets the 15min timer; while in 32s mode, Setting CD=1
will NOT reset the 32-second timer.
Boost mode enable control or input current limiting selection pin. When OTG is in active status, bq24153A/8
is forced to operate in boost mode. It has higher priority over I2C control and can be disabled using the
OTG
D4
I
control register. At POR while in 15-min mode, the OTG pin is default to be used as the input current limiting
(bq24153A/8 only)
selection pin. The I2C register is ignored at startup. When OTG=High, IIN_LIMIT=500mA and when OTG=Low,
IIN_LIMIT=100mA.
Safety limit register reset control. When SLRST=0, bq24156A/9 resets all the safety limits (06H) to default
SLRST
D4
I
values, regardless of the write actions to safety limits registers (06H). When SLRST=1, bq24156A/9 can
(bq24156A/9 only)
program the safety limit register until any write action to other registers locks the programmed safety limits.
Copyright
© 2010–2012, Texas Instruments Incorporated
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Product Folder Link(s): bq24153A bq24156A bq24158 bq24159


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